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| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-07-02 11:51:10 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-05 09:56:03 +0200 |
| commit | 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a (patch) | |
| tree | 72c827f18f745eb95167f637820f46bcd1b83c11 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | cad2a2d7761238c0b9ff62eecc89215e6bd61831 (diff) | |
| download | blackbird-op-linux-1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a.tar.gz blackbird-op-linux-1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a.zip | |
drm/i915: enable RC6 workaround on Haswell
For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.
v2: add comment saying that this is for early revisions only.
v3: beautify as suggested by Daniel Vetter.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3c2724e42975..6e02698e9a3d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3467,6 +3467,16 @@ static void haswell_init_clock_gating(struct drm_device *dev) /* WaDisable4x2SubspanOptimization */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); + + /* XXX: This is a workaround for early silicon revisions and should be + * removed later. + */ + I915_WRITE(WM_DBG, + I915_READ(WM_DBG) | + WM_DBG_DISALLOW_MULTIPLE_LP | + WM_DBG_DISALLOW_SPRITE | + WM_DBG_DISALLOW_MAXFIFO); + } static void ivybridge_init_clock_gating(struct drm_device *dev) |
