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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-08-02 16:22:25 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-08-22 13:31:48 +0200 |
| commit | 6aedd1f539f51b7b0c3d6be0088c3541f9d2c294 (patch) | |
| tree | 687316402b6b7e401fc018f0c4890b7c549a9fa1 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 8dc8a27c9733a41cda84e8c70da8313e1d54c4ae (diff) | |
| download | blackbird-op-linux-6aedd1f539f51b7b0c3d6be0088c3541f9d2c294.tar.gz blackbird-op-linux-6aedd1f539f51b7b0c3d6be0088c3541f9d2c294.zip | |
drm/i915: clarify Haswell power well bit names
Whenever I need to work with the HSW_PWER_WELL_* register bits I have
to look at the documentation to find out which bit is to request the
power well and which one shows its current state. Rename the bits so I
won't need to look the docs every time.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fab94be89dfa..3c652eb7ee6c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4825,8 +4825,8 @@ #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ -#define HSW_PWR_WELL_ENABLE (1<<31) -#define HSW_PWR_WELL_STATE (1<<30) +#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) +#define HSW_PWR_WELL_STATE_ENABLED (1<<30) #define HSW_PWR_WELL_CTL5 0x45410 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) |
