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authorDave Airlie <airlied@redhat.com>2012-10-03 10:32:58 +1000
committerDave Airlie <airlied@redhat.com>2012-10-03 10:32:58 +1000
commit8ff1f792dd68ad46f3cfe01e01a375b402cf08da (patch)
treeb73b4fa71c5a9357931360d7894beee247cd464e /drivers/gpu/drm/drm_irq.c
parent2216c9e74fb3baac3cb73952158dbe38b703997e (diff)
parent82ffd92b162ece87c863c075d993c65333e8e78b (diff)
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Merge branch 'drm-next-3.7' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes: "The big changes for 3.7 include: - Asynchronous VM page table updates for Cayman/SI - 2 level VM page table support. Saves memory compared to 1 level page tables. - Reworked PLL handing in the display code allows lots more combinations of monitors to work, including more than two DP displays assuming compatible clocks across shared PLLs. This also allows us to power down extra PLLs when we can share a single one across multiple displays which saves power. - Native backlight control on ATOMBIOS systems. - Improved ACPI support for interacting with the GPU. Fixes backlight control on some laptops. - Document AMD ACPI interfaces - Lots of code cleanup - Bug fixes" * 'drm-next-3.7' of git://people.freedesktop.org/~agd5f/linux: (79 commits) drm/radeon: add vm set_page() callback for SI drm/radeon: rework the vm_flush interface drm/radeon: use WRITE_DATA packets for vm flush on SI drm/radeon/pm: fix multi-head profile handling on BTC+ (v2) drm/radeon: fix radeon power state debug output drm/radeon: force MSIs on RS690 asics drm/radeon: Add MSI quirk for gateway RS690 drm/radeon: allow MIP_ADDRESS=0 for MSAA textures on Evergreen drm/radeon/kms: allow STRMOUT_BASE_UPDATE on RS780 and RS880 drm/radeon: add 2-level VM pagetables support v9 drm/radeon: refactor set_page chipset interface v5 drm/radeon: Fix scratch register leak in IB test. drm/radeon: restore backlight level on resume drm/radeon: add get_backlight_level callback drm/radeon: only adjust default clocks on NI GPUs drm/radeon: validate PPLL in crtc fixup drm/radeon: work around KMS modeset limitations in PLL allocation (v2) drm/radeon: make non-DP PPLL sharing more robust drm/radeon: store the encoder in the radeon_crtc drm/radeon: rework crtc pll setup to better support PPLL sharing ...
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