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authorBruce Allan <bruce.w.allan@intel.com>2010-07-27 12:28:46 +0000
committerDavid S. Miller <davem@davemloft.net>2010-07-27 21:06:26 -0700
commitff847ac2d3e90edd94674c28bade25ae1e6a2e49 (patch)
tree739943e28d858421e40feca4e99eaed10f3c6ebe /drivers/ata/libahci.c
parent5447080cfa3c77154498dfbf225367ac85b4c2b5 (diff)
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e1000e: 82577/82578 PHY register access issues
The MAC-PHY interconnect on 82577/82578 uses a power management feature (called K1) which must be disabled when in 1Gbps due to a hardware issue on these parts. The #define bit setting used to enable/disable K1 is incorrect and can cause PHY register accesses to stop working altogether until the next device reset. This patch sets the register correctly. This issue is present in kernels since 2.6.32. CC: stable@kernel.org Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ata/libahci.c')
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