diff options
| author | Will Deacon <will.deacon@arm.com> | 2012-11-15 21:28:43 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2012-11-15 21:39:34 +0000 |
| commit | f600b9fcd2bcb8ee0adb235f54ccdd93c729c442 (patch) | |
| tree | ece27e6ac0d2b7b27bf8f365990e5af39bd8eef1 /arch | |
| parent | f435ab79928e4d54082e2838c4562a165e37999c (diff) | |
| download | blackbird-op-linux-f600b9fcd2bcb8ee0adb235f54ccdd93c729c442.tar.gz blackbird-op-linux-f600b9fcd2bcb8ee0adb235f54ccdd93c729c442.zip | |
ARM: cti: fix manipulation of debug lock registers
The LOCKSTATUS register for memory-mapped coresight devices indicates
whether or not the device in question implements hardware locking. If
not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore,
so software doesn't actually need to check the status register at all.
This patch removes the broken LSR checks.
Cc: Ming Lei <ming.lei@canonical.com>
Reported-by: Mike Williams <michael.williams@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/cti.h | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h index a0ada3ea4358..f2e5cad3f306 100644 --- a/arch/arm/include/asm/cti.h +++ b/arch/arm/include/asm/cti.h @@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti) */ static inline void cti_unlock(struct cti *cti) { - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + LOCKSTATUS); - - if (val & 1) { - val = LOCKCODE; - __raw_writel(val, base + LOCKACCESS); - } + __raw_writel(LOCKCODE, cti->base + LOCKACCESS); } /** @@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti) */ static inline void cti_lock(struct cti *cti) { - void __iomem *base = cti->base; - unsigned long val; - - val = __raw_readl(base + LOCKSTATUS); - - if (!(val & 1)) { - val = ~LOCKCODE; - __raw_writel(val, base + LOCKACCESS); - } + __raw_writel(~LOCKCODE, cti->base + LOCKACCESS); } #endif |
