diff options
| author | Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> | 2008-02-22 23:10:16 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-04-17 17:40:49 +0200 |
| commit | e0f025704437dfd6cb5adc077f05709c31189edc (patch) | |
| tree | 092ce378d0ae1de341f502dd04aaf9bfb8126dab /arch | |
| parent | 0067cc996ee7a0dd282d8da5b64fa60aa2066bb2 (diff) | |
| download | blackbird-op-linux-e0f025704437dfd6cb5adc077f05709c31189edc.tar.gz blackbird-op-linux-e0f025704437dfd6cb5adc077f05709c31189edc.zip | |
x86: coding style fixes to arch/x86/kernel/cpu/mtrr/state.c
Before:
total: 6 errors, 5 warnings, 80 lines checked
After:
total: 0 errors, 4 warnings, 82 lines checked
No code changed:
arch/x86/kernel/cpu/mtrr/state.o:
text data bss dec hex filename
313 0 4 317 13d state.o.before
313 0 4 317 13d state.o.after
md5:
a0fbd61096205f9180f0bf45ed386d61 state.o.before.asm
a0fbd61096205f9180f0bf45ed386d61 state.o.after.asm
Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/cpu/mtrr/state.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/x86/kernel/cpu/mtrr/state.c b/arch/x86/kernel/cpu/mtrr/state.c index 9f8ba923d1c9..7f7e2753685b 100644 --- a/arch/x86/kernel/cpu/mtrr/state.c +++ b/arch/x86/kernel/cpu/mtrr/state.c @@ -19,13 +19,15 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) if (use_intel() || is_cpu(CYRIX)) { /* Save value of CR4 and clear Page Global Enable (bit 7) */ - if ( cpu_has_pge ) { + if (cpu_has_pge) { ctxt->cr4val = read_cr4(); write_cr4(ctxt->cr4val & ~X86_CR4_PGE); } - /* Disable and flush caches. Note that wbinvd flushes the TLBs as - a side-effect */ + /* + * Disable and flush caches. Note that wbinvd flushes the TLBs + * as a side-effect + */ cr0 = read_cr0() | X86_CR0_CD; wbinvd(); write_cr0(cr0); @@ -42,7 +44,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) void set_mtrr_cache_disable(struct set_mtrr_context *ctxt) { - if (use_intel()) + if (use_intel()) /* Disable MTRRs, and set the default type to uncached */ mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL, ctxt->deftype_hi); @@ -66,12 +68,12 @@ void set_mtrr_done(struct set_mtrr_context *ctxt) else /* Cyrix ARRs - everything else was excluded at the top */ setCx86(CX86_CCR3, ctxt->ccr3); - + /* Enable caches */ write_cr0(read_cr0() & 0xbfffffff); /* Restore value of CR4 */ - if ( cpu_has_pge ) + if (cpu_has_pge) write_cr4(ctxt->cr4val); } /* Re-enable interrupts locally (if enabled previously) */ |
