diff options
| author | Rahul Sharma <rahul.sharma@samsung.com> | 2014-07-16 08:37:00 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2014-07-16 08:37:00 +0900 |
| commit | d51cad7df87119ab625ad8ba15eb3e8f9ea44fc9 (patch) | |
| tree | 99ad67f5ff0c8da39120b66fe3f1b075b65fe0cc /arch | |
| parent | 5a852743a495b8628ad6c848a74254ec8fcc9c27 (diff) | |
| download | blackbird-op-linux-d51cad7df87119ab625ad8ba15eb3e8f9ea44fc9.tar.gz blackbird-op-linux-d51cad7df87119ab625ad8ba15eb3e8f9ea44fc9.zip | |
ARM: dts: remove display power domain for exynos5420
Display domain is removed due to instability issues. Explaining
the problem below:
exynos_init_late triggers the pm_genpd_poweroff_unused which powers
off the unused power domains. This call hits before the trigger to
deferred probes.
DRM DP Panel defers the probe due to supply get failure. By the time,
deferred probe is scheduled again, Display Power Domain is powered
off by pm_genpd_poweroff_unused.
FIMD and DP drivers are accessing registers during Probe and Bind
callbacks. If display domain is enabled/disabled around register
accesses, display domain gets unstable and we are getting Power Domain
Disable fail notification. Increasing the Timeout also didn't help.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e38532271ef9..3d528cffe943 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -262,11 +262,6 @@ reg = <0x10044060 0x20>; }; - disp_pd: power-domain@100440C0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; - }; - msc_pd: power-domain@10044120 { compatible = "samsung,exynos4210-pd"; reg = <0x10044120 0x20>; @@ -518,7 +513,6 @@ }; fimd: fimd@14400000 { - samsung,power-domain = <&disp_pd>; clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; |
