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authorBenoit Cousson <b-cousson@ti.com>2011-03-10 10:53:15 +0100
committerBenoit Cousson <b-cousson@ti.com>2011-03-10 11:04:00 +0100
commitb9ccf8afe2d2eafe18f90d2925f8464313fe0b56 (patch)
treed6fc73de26b1344736a59965b336bb7c6b245a31 /arch
parent0dde52a9f5330eec240660191a94b51bd911ffcd (diff)
downloadblackbird-op-linux-b9ccf8afe2d2eafe18f90d2925f8464313fe0b56.tar.gz
blackbird-op-linux-b9ccf8afe2d2eafe18f90d2925f8464313fe0b56.zip
OMAP3: hwmod data: Fix incorrect SmartReflex -> L4 CORE interconnect links
Commit d34427267186827dfd62bd8cf726601fffb22534 ("OMAP3: PM: Adding smartreflex hwmod data") added data that claims that the L4 CORE has two slave interfaces that originate from the SmartReflex modules, omap3_l4_core__sr1 and omap3_l4_core__sr2. But as those two data structure records show, it's L4 CORE that has a master port towards SR1 and SR2. Move the incorrect data from slaves list to master list. Based on a path by Paul Walmsley <paul@pwsan.com> https://patchwork.kernel.org/patch/623171/ That is based on a patch by Benoît Cousson <b-cousson@ti.com>: https://patchwork.kernel.org/patch/590561/ Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Cc: Sanjeev Premi <premi@ti.com> Cc: Thara Gopinath <thara@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c4ca005f8bb5..dec329ff0924 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -491,8 +491,6 @@ static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
&omap3xxx_l3_main__l4_core,
- &omap3_l4_core__sr1,
- &omap3_l4_core__sr2,
};
/* Master interfaces on the L4_CORE interconnect */
@@ -503,6 +501,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
&omap3_l4_core__i2c1,
&omap3_l4_core__i2c2,
&omap3_l4_core__i2c3,
+ &omap3_l4_core__sr1,
+ &omap3_l4_core__sr2,
};
/* L4 CORE */
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