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authorMark A. Greer <mgreer@animalcreek.com>2012-04-30 16:57:09 -0700
committerKevin Hilman <khilman@ti.com>2012-05-11 16:47:19 -0700
commit1ce029968718477149e7f1fb245a8e82c690cc4a (patch)
treeb86b1a0bd788cd7e0e7f759bcf71ad96df6e1bb0 /arch
parent99b59df04899a048d1a3ed8bc2b1263779816868 (diff)
downloadblackbird-op-linux-1ce029968718477149e7f1fb245a8e82c690cc4a.tar.gz
blackbird-op-linux-1ce029968718477149e7f1fb245a8e82c690cc4a.zip
arm: omap3: am35x: Don't mark missing features as present
The Chip Identification register on the am35x family of SoCs has bits 12, 7:5, and 3:2 marked as reserved and are read as zeroes. Unfortunately, on other omap SoCs, a 0 bit means a feature is "Full Use" so the OMAP3_CHECK_FEATURE() macro called by omap3_check_features() will incorrectly interpret those zeroes to mean that a feature is present even though it isn't. To fix that, the feature bits that are incorrectly set (namely, OMAP3_HAS_IVA and OMAP3_HAS_ISP) need to be cleared after all of the calls to OMAP3_CHECK_FEATURE() in omap3_check_features() are made. Signed-off-by: Mark A. Greer <mgreer@animalcreek.com> [khilman@ti.com: use soc_is_am35xx() instead of cpu_is_am35xx()] Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/id.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index f611e3097157..38ae74f8e77a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -247,6 +247,17 @@ void __init omap3xxx_check_features(void)
omap_features |= OMAP3_HAS_SDRC;
/*
+ * am35x fixups:
+ * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
+ * reserved and therefore return 0 when read. Unfortunately,
+ * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
+ * mean that a feature is present even though it isn't so clear
+ * the incorrectly set feature bits.
+ */
+ if (soc_is_am35xx())
+ omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
+
+ /*
* TODO: Get additional info (where applicable)
* e.g. Size of L2 cache.
*/
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