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authorH. Peter Anvin <hpa@zytor.com>2012-07-20 13:35:06 -0700
committerH. Peter Anvin <hpa@zytor.com>2012-07-20 13:36:41 -0700
commit30d5c4546a7dae29a1aa76abdb69a78bb00136be (patch)
tree9d24604b6c920e44dd582498b3c991b7b6a5faa7 /arch/x86/include
parent84a1caf1453c3d44050bd22db958af4a7f99315c (diff)
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x86, cpufeature: Add the RDSEED and ADX features
Add the RDSEED and ADX features documented in section 9.1 of the Intel Architecture Instruction Set Extensions Programming Reference, document 319433, version 013b, available from http://software.intel.com/en-us/avx/ The PREFETCHW bit is already supported in Linux under the name 3DNOWPREFETCH. Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/n/tip-lgr6482ufk1bvxzvc2hr8qbp@git.kernel.org
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/cpufeature.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index f91e80f4f180..6b7ee5ff6820 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -207,6 +207,8 @@
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
+#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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