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authorKan Liang <Kan.liang@intel.com>2017-09-08 17:34:48 -0400
committerThomas Gleixner <tglx@linutronix.de>2017-09-25 09:36:17 +0200
commit1aaccc40a1864053da26605b0297be16dd52641e (patch)
treef9611311989f8dfd59233db64a191cdb9e724592 /arch/x86/events/intel/rapl.c
parentb09c146f8f63c0e03adba74df76bf9c2be466fec (diff)
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perf/x86/msr: Add missing CPU IDs
Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well. Signed-off-by: Kan Liang <Kan.liang@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: ak@linux.intel.com Cc: peterz@infradead.org Cc: piotr.luc@intel.com Cc: harry.pan@intel.com Cc: srinivas.pandruvada@linux.intel.com Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com
Diffstat (limited to 'arch/x86/events/intel/rapl.c')
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