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| author | David S. Miller <davem@sunset.davemloft.net> | 2006-02-01 15:55:21 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 01:11:32 -0800 |
| commit | 517af33237ecfc3c8a93b335365fa61e741ceca4 (patch) | |
| tree | 58eff40eb4c517c4fd49fd347d38273ee1e1ee4b /arch/sparc64/kernel/itlb_miss.S | |
| parent | b0fd4e49aea8a460afab7bc67cd618e2d19291d4 (diff) | |
| download | blackbird-op-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.tar.gz blackbird-op-linux-517af33237ecfc3c8a93b335365fa61e741ceca4.zip | |
[SPARC64]: Access TSB with physical addresses when possible.
This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section. The default uses
virtual addresses, and the patch instructions use physical
address load/stores.
We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/itlb_miss.S')
| -rw-r--r-- | arch/sparc64/kernel/itlb_miss.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc64/kernel/itlb_miss.S b/arch/sparc64/kernel/itlb_miss.S index 6b6c8fee04bd..97facce27aad 100644 --- a/arch/sparc64/kernel/itlb_miss.S +++ b/arch/sparc64/kernel/itlb_miss.S @@ -4,7 +4,7 @@ srlx %g6, 48, %g5 ! Get context brz,pn %g5, kvmap_itlb ! Context 0 processing nop ! Delay slot (fill me) - ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 ! Load TSB entry + TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry cmp %g4, %g6 ! Compare TAG sethi %hi(_PAGE_EXEC), %g4 ! Setup exec check |
