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authorSam Ravnborg <sam@ravnborg.org>2008-12-03 03:11:52 -0800
committerDavid S. Miller <davem@davemloft.net>2008-12-04 09:17:21 -0800
commita88b5ba8bd8ac18aad65ee6c6a254e2e74876db3 (patch)
treeeb3d0ffaf53c3f7ec6083752c2097cecd1cb892a /arch/sparc/kernel/pci_sun4v_asm.S
parentd670bd4f803c8b646acd20f3ba21e65458293faf (diff)
downloadblackbird-op-linux-a88b5ba8bd8ac18aad65ee6c6a254e2e74876db3.tar.gz
blackbird-op-linux-a88b5ba8bd8ac18aad65ee6c6a254e2e74876db3.zip
sparc,sparc64: unify kernel/
o Move all files from sparc64/kernel/ to sparc/kernel - rename as appropriate o Update sparc/Makefile to the changes o Update sparc/kernel/Makefile to include the sparc64 files NOTE: This commit changes link order on sparc64! Link order had to change for either of sparc32 and sparc64. And assuming sparc64 see more testing than sparc32 change link order on sparc64 where issues will be caught faster. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/pci_sun4v_asm.S')
-rw-r--r--arch/sparc/kernel/pci_sun4v_asm.S362
1 files changed, 362 insertions, 0 deletions
diff --git a/arch/sparc/kernel/pci_sun4v_asm.S b/arch/sparc/kernel/pci_sun4v_asm.S
new file mode 100644
index 000000000000..e606d46c6815
--- /dev/null
+++ b/arch/sparc/kernel/pci_sun4v_asm.S
@@ -0,0 +1,362 @@
+/* pci_sun4v_asm: Hypervisor calls for PCI support.
+ *
+ * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
+ */
+
+#include <linux/linkage.h>
+#include <asm/hypervisor.h>
+
+ /* %o0: devhandle
+ * %o1: tsbid
+ * %o2: num ttes
+ * %o3: io_attributes
+ * %o4: io_page_list phys address
+ *
+ * returns %o0: -status if status was non-zero, else
+ * %o0: num pages mapped
+ */
+ENTRY(pci_sun4v_iommu_map)
+ mov %o5, %g1
+ mov HV_FAST_PCI_IOMMU_MAP, %o5
+ ta HV_FAST_TRAP
+ brnz,pn %o0, 1f
+ sub %g0, %o0, %o0
+ mov %o1, %o0
+1: retl
+ nop
+ENDPROC(pci_sun4v_iommu_map)
+
+ /* %o0: devhandle
+ * %o1: tsbid
+ * %o2: num ttes
+ *
+ * returns %o0: num ttes demapped
+ */
+ENTRY(pci_sun4v_iommu_demap)
+ mov HV_FAST_PCI_IOMMU_DEMAP, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o1, %o0
+ENDPROC(pci_sun4v_iommu_demap)
+
+ /* %o0: devhandle
+ * %o1: tsbid
+ * %o2: &io_attributes
+ * %o3: &real_address
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_iommu_getmap)
+ mov %o2, %o4
+ mov HV_FAST_PCI_IOMMU_GETMAP, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o4]
+ stx %o2, [%o3]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_iommu_getmap)
+
+ /* %o0: devhandle
+ * %o1: pci_device
+ * %o2: pci_config_offset
+ * %o3: size
+ *
+ * returns %o0: data
+ *
+ * If there is an error, the data will be returned
+ * as all 1's.
+ */
+ENTRY(pci_sun4v_config_get)
+ mov HV_FAST_PCI_CONFIG_GET, %o5
+ ta HV_FAST_TRAP
+ brnz,a,pn %o1, 1f
+ mov -1, %o2
+1: retl
+ mov %o2, %o0
+ENDPROC(pci_sun4v_config_get)
+
+ /* %o0: devhandle
+ * %o1: pci_device
+ * %o2: pci_config_offset
+ * %o3: size
+ * %o4: data
+ *
+ * returns %o0: status
+ *
+ * status will be zero if the operation completed
+ * successfully, else -1 if not
+ */
+ENTRY(pci_sun4v_config_put)
+ mov HV_FAST_PCI_CONFIG_PUT, %o5
+ ta HV_FAST_TRAP
+ brnz,a,pn %o1, 1f
+ mov -1, %o1
+1: retl
+ mov %o1, %o0
+ENDPROC(pci_sun4v_config_put)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: msiq phys address
+ * %o3: num entries
+ *
+ * returns %o0: status
+ *
+ * status will be zero if the operation completed
+ * successfully, else -1 if not
+ */
+ENTRY(pci_sun4v_msiq_conf)
+ mov HV_FAST_PCI_MSIQ_CONF, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_conf)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: &msiq_phys_addr
+ * %o3: &msiq_num_entries
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_info)
+ mov %o2, %o4
+ mov HV_FAST_PCI_MSIQ_INFO, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o4]
+ stx %o2, [%o3]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_info)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: &valid
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_getvalid)
+ mov HV_FAST_PCI_MSIQ_GETVALID, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_getvalid)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: valid
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_setvalid)
+ mov HV_FAST_PCI_MSIQ_SETVALID, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_setvalid)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: &state
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_getstate)
+ mov HV_FAST_PCI_MSIQ_GETSTATE, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_getstate)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: state
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_setstate)
+ mov HV_FAST_PCI_MSIQ_SETSTATE, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_setstate)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: &head
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_gethead)
+ mov HV_FAST_PCI_MSIQ_GETHEAD, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_gethead)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: head
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_sethead)
+ mov HV_FAST_PCI_MSIQ_SETHEAD, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_sethead)
+
+ /* %o0: devhandle
+ * %o1: msiqid
+ * %o2: &tail
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msiq_gettail)
+ mov HV_FAST_PCI_MSIQ_GETTAIL, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msiq_gettail)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: &valid
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msi_getvalid)
+ mov HV_FAST_PCI_MSI_GETVALID, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msi_getvalid)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: valid
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msi_setvalid)
+ mov HV_FAST_PCI_MSI_SETVALID, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msi_setvalid)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: &msiq
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msi_getmsiq)
+ mov HV_FAST_PCI_MSI_GETMSIQ, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msi_getmsiq)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: msitype
+ * %o3: msiq
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msi_setmsiq)
+ mov HV_FAST_PCI_MSI_SETMSIQ, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msi_setmsiq)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: &state
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msi_getstate)
+ mov HV_FAST_PCI_MSI_GETSTATE, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msi_getstate)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: state
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msi_setstate)
+ mov HV_FAST_PCI_MSI_SETSTATE, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msi_setstate)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: &msiq
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msg_getmsiq)
+ mov HV_FAST_PCI_MSG_GETMSIQ, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msg_getmsiq)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: msiq
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msg_setmsiq)
+ mov HV_FAST_PCI_MSG_SETMSIQ, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msg_setmsiq)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: &valid
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msg_getvalid)
+ mov HV_FAST_PCI_MSG_GETVALID, %o5
+ ta HV_FAST_TRAP
+ stx %o1, [%o2]
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msg_getvalid)
+
+ /* %o0: devhandle
+ * %o1: msinum
+ * %o2: valid
+ *
+ * returns %o0: status
+ */
+ENTRY(pci_sun4v_msg_setvalid)
+ mov HV_FAST_PCI_MSG_SETVALID, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o0, %o0
+ENDPROC(pci_sun4v_msg_setvalid)
+
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