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authorMagnus Damm <damm@opensource.se>2010-05-11 09:35:55 +0000
committerPaul Mundt <lethal@linux-sh.org>2010-05-13 17:36:34 +0900
commit59aa69d9c20b1ee15fa26aa6631b555aaef91323 (patch)
treeb95b2d6ad2c09ac6fef4d5b25245e27240f22f59 /arch/sh/kernel/cpu/sh4a
parent8249a3113094b826c5010d27c8cf07a395be2abc (diff)
downloadblackbird-op-linux-59aa69d9c20b1ee15fa26aa6631b555aaef91323.tar.gz
blackbird-op-linux-59aa69d9c20b1ee15fa26aa6631b555aaef91323.zip
sh: switch sh7366 to clkdev
This patch converts the remaining sh7366 clocks to use clkdev for lookup. The now unused name and id from struct clk are also removed. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 4c3a5a583012..7ce5bbcd4084 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -37,8 +37,6 @@
/* Fixed 32 KHz root clock for RTC and Power Management purposes */
static struct clk r_clk = {
- .name = "rclk",
- .id = -1,
.rate = 32768,
};
@@ -47,8 +45,6 @@ static struct clk r_clk = {
* from the platform code.
*/
struct clk extal_clk = {
- .name = "extal",
- .id = -1,
.rate = 33333333,
};
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
};
static struct clk dll_clk = {
- .name = "dll_clk",
- .id = -1,
.ops = &dll_clk_ops,
.parent = &r_clk,
.flags = CLK_ENABLE_ON_INIT,
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
};
static struct clk pll_clk = {
- .name = "pll_clk",
- .id = -1,
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
};
@@ -203,6 +195,12 @@ static struct clk mstp_clks[MSTP_NR] = {
#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
static struct clk_lookup lookups[] = {
+ /* main clocks */
+ CLKDEV_CON_ID("rclk", &r_clk),
+ CLKDEV_CON_ID("extal", &extal_clk),
+ CLKDEV_CON_ID("dll_clk", &dll_clk),
+ CLKDEV_CON_ID("pll_clk", &pll_clk),
+
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
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