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| author | Scott Wood <scottwood@freescale.com> | 2007-11-25 13:09:31 +0300 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-12-13 22:45:35 -0600 |
| commit | 0b5cf10691eb2c95a9126bf25f5e084d83d5d743 (patch) | |
| tree | 5b3e861e4247b080067070d11d238705c03e38ed /arch/powerpc/platforms/8xx/mpc86xads.h | |
| parent | 77d4309e19b1a7ab3286cd741e924894fc329986 (diff) | |
| download | blackbird-op-linux-0b5cf10691eb2c95a9126bf25f5e084d83d5d743.tar.gz blackbird-op-linux-0b5cf10691eb2c95a9126bf25f5e084d83d5d743.zip | |
[POWERPC] 8xx: Convert mpc866ads to the new device binding.
Verified on mpc866ads. This version has muram and brg nodes added to dts
to get the things work.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/platforms/8xx/mpc86xads.h')
| -rw-r--r-- | arch/powerpc/platforms/8xx/mpc86xads.h | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/arch/powerpc/platforms/8xx/mpc86xads.h b/arch/powerpc/platforms/8xx/mpc86xads.h index cffa194ccf1f..17b1fe75e0b2 100644 --- a/arch/powerpc/platforms/8xx/mpc86xads.h +++ b/arch/powerpc/platforms/8xx/mpc86xads.h @@ -15,27 +15,6 @@ #ifndef __ASM_MPC86XADS_H__ #define __ASM_MPC86XADS_H__ -#include <sysdev/fsl_soc.h> - -/* U-Boot maps BCSR to 0xff080000 */ -#define BCSR_ADDR ((uint)0xff080000) -#define BCSR_SIZE ((uint)32) -#define BCSR0 ((uint)(BCSR_ADDR + 0x00)) -#define BCSR1 ((uint)(BCSR_ADDR + 0x04)) -#define BCSR2 ((uint)(BCSR_ADDR + 0x08)) -#define BCSR3 ((uint)(BCSR_ADDR + 0x0c)) -#define BCSR4 ((uint)(BCSR_ADDR + 0x10)) - -#define CFG_PHYDEV_ADDR ((uint)0xff0a0000) -#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300)) - -#define MPC8xx_CPM_OFFSET (0x9c0) -#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET) -#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - /* Bits of interest in the BCSRs. */ #define BCSR1_ETHEN ((uint)0x20000000) @@ -64,28 +43,5 @@ #define BCSR5_MII1_EN 0x02 #define BCSR5_MII1_RST 0x01 -/* Interrupt level assignments */ -#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */ -#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */ -#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */ - -/* We don't use the 8259 */ -#define NR_8259_INTS 0 - -/* CPM Ethernet through SCC1 */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) - #endif /* __ASM_MPC86XADS_H__ */ #endif /* __KERNEL__ */ |
