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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-01-07 15:53:29 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-04-06 09:09:14 -0500 |
| commit | d91e4ea7047d96733d763f1626f1f21ff4298cef (patch) | |
| tree | fa017e48c9f523ce16b59668ac1be6c75f9e3618 /arch/powerpc/include | |
| parent | e60f57f50f861f29052e0e3563ac453da53f2181 (diff) | |
| download | blackbird-op-linux-d91e4ea7047d96733d763f1626f1f21ff4298cef.tar.gz blackbird-op-linux-d91e4ea7047d96733d763f1626f1f21ff4298cef.zip | |
powerpc: Add support for CoreInt delivery of interrupts on MPIC
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to provide an improvment
in interrupt latency by reducing the time to get the IRQ vector.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/mpic.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index c2ccca53b991..a002682f3a6d 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -22,6 +22,14 @@ #define MPIC_GREG_FEATURE_1 0x00010 #define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GCONF_RESET 0x80000000 +/* On the FSL mpic implementations the Mode field is expand to be + * 2 bits wide: + * 0b00 = pass through (interrupts routed to IRQ0) + * 0b01 = Mixed mode + * 0b10 = reserved + * 0b11 = External proxy / coreint + */ +#define MPIC_GREG_GCONF_COREINT 0x60000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff @@ -357,6 +365,8 @@ struct mpic #define MPIC_BROKEN_FRR_NIRQS 0x00000800 /* Destination only supports a single CPU at a time */ #define MPIC_SINGLE_DEST_CPU 0x00001000 +/* Enable CoreInt delivery of interrupts */ +#define MPIC_ENABLE_COREINT 0x00002000 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 @@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq); extern unsigned int mpic_get_one_irq(struct mpic *mpic); /* This one gets from the primary mpic */ extern unsigned int mpic_get_irq(void); +/* This one gets from the primary mpic via CoreInt*/ +extern unsigned int mpic_get_coreint_irq(void); /* Fetch Machine Check interrupt from primary mpic */ extern unsigned int mpic_get_mcirq(void); |
