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authorPaul Mackerras <paulus@samba.org>2009-02-23 23:01:28 +1100
committerPaul Mackerras <paulus@samba.org>2009-02-23 23:01:28 +1100
commitd095cd46dac104e4d2a4967c7c19b55a12f78240 (patch)
tree032528a3e23b2fe1b8998e7064101394108ce870 /arch/powerpc/include/asm/bug.h
parentcebb469ba242f7ce476e378c8cd3b0c6c63a4c54 (diff)
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perfcounters/powerpc: Make exclude_kernel bit work on Apple G5 processors
Currently, setting hw_event.exclude_kernel does nothing on the PPC970 variants used in Apple G5 machines, because they have the HV (hypervisor) bit in the MSR forced to 1, so as far as the PMU is concerned, the kernel runs in hypervisor mode. Thus we have to use the MMCR0_FCHV (freeze counters in hypervisor mode) bit rather than the MMCR0_FCS (freeze counters in supervisor mode) bit. This checks the MSR.HV bit at startup, and if it is set, we set the freeze_counters_kernel variable to MMCR0_FCHV (it was initialized to MMCR0_FCS). We then use that whenever we need to exclude kernel events. Signed-off-by: Paul Mackerras <paulus@samba.org>
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