diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2007-08-16 23:55:55 -0500 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-08-17 13:22:16 -0500 |
commit | b66510cb9992d204f216049e9c01d432c7635f6c (patch) | |
tree | 4b00de7786b1ae5aeab06692fe2f67e1d8667fe7 /arch/powerpc/boot/dts/mpc8544ds.dts | |
parent | ada3ea6fcde45abc55e2af0e564455fd7f943a79 (diff) | |
download | blackbird-op-linux-b66510cb9992d204f216049e9c01d432c7635f6c.tar.gz blackbird-op-linux-b66510cb9992d204f216049e9c01d432c7635f6c.zip |
[POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards
The interrupt routing in the device trees for the ULI M1575 was
inproperly using the interrupt line field as pci function. Fixed
up the device tree's to actual conform for to specification and
changed the interrupt mapping code so it just uses a static mapping
setup as follows:
PIRQA - IRQ9
PIRQB - IRQ10
PIRQC - IRQ11
PIRQD - IRQ12
USB 1.1 OCHI (1c.0) - IRQ12
USB 1.1 OCHI (1c.1) - IRQ9
USB 1.1 OCHI (1c.2) - IRQ10
USB 1.1 ECHI (1c.3) - IRQ11
LAN (1b.0) - IRQ6
AC97 (1d.0) - IRQ6
Modem (1d.1) - IRQ6
HD Audio (1d.2) - IRQ6
SATA (1f.1) - IRQ5
SMB (1e.1) - IRQ7
PMU (1e.2) - IRQ7
PATA (1f.0) - IRQ14/15
Took the oppurtunity to refactor the code into a single file so we
don't have to duplicate these fixes on the two current boards in the
tree and several forth coming boards that will also need the code.
Fixed RTC support that requires a dummy memory read on the P2P bridge
to unlock the RTC and setup the default of the RTC alarm registers to
match with a basic x86 style CMOS RTC.
Moved code that poked ISA registers to a FIXUP_FINAL quirk to ensure
the PCI IO space has been setup properly before we start poking ISA
registers at random locations.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8544ds.dts')
-rw-r--r-- | arch/powerpc/boot/dts/mpc8544ds.dts | 88 |
1 files changed, 38 insertions, 50 deletions
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts index 4680e2010887..3e79bf0a3159 100644 --- a/arch/powerpc/boot/dts/mpc8544ds.dts +++ b/arch/powerpc/boot/dts/mpc8544ds.dts @@ -44,8 +44,18 @@ #size-cells = <1>; #interrupt-cells = <2>; device_type = "soc"; - ranges = <0 e0000000 00100000>; - reg = <e0000000 00100000>; // CCSRBAR 1M + + + ranges = <00001000 e0001000 000ff000 + 80000000 80000000 20000000 + a0000000 a0000000 10000000 + b0000000 b0000000 00100000 + c0000000 c0000000 20000000 + b0100000 b0100000 00100000 + e1000000 e1000000 00010000 + e1010000 e1010000 00010000 + e1020000 e1020000 00010000>; + reg = <e0000000 00001000>; // CCSRBAR 1M bus-frequency = <0>; // Filled out by uboot. memory-controller@2000 { @@ -161,8 +171,8 @@ interrupt-parent = <&mpic>; interrupts = <18 2>; bus-range = <0 ff>; - ranges = <02000000 0 80000000 80000000 0 10000000 - 01000000 0 00000000 e2000000 0 00800000>; + ranges = <02000000 0 c0000000 c0000000 0 20000000 + 01000000 0 00000000 e1000000 0 00010000>; clock-frequency = <3f940aa>; #interrupt-cells = <1>; #size-cells = <2>; @@ -178,8 +188,8 @@ #address-cells = <3>; reg = <9000 1000>; bus-range = <0 ff>; - ranges = <02000000 0 90000000 90000000 0 10000000 - 01000000 0 00000000 e3000000 0 00800000>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e1010000 0 00010000>; clock-frequency = <1fca055>; interrupt-parent = <&mpic>; interrupts = <1a 2>; @@ -202,7 +212,7 @@ reg = <a000 1000>; bus-range = <0 ff>; ranges = <02000000 0 a0000000 a0000000 0 10000000 - 01000000 0 00000000 e2800000 0 00800000>; + 01000000 0 00000000 e1020000 0 00010000>; clock-frequency = <1fca055>; interrupt-parent = <&mpic>; interrupts = <19 2>; @@ -224,49 +234,29 @@ #address-cells = <3>; reg = <b000 1000>; bus-range = <0 ff>; - ranges = <02000000 0 b0000000 b0000000 0 10000000 - 01000000 0 00000000 e3800000 0 00800000>; + ranges = <02000000 0 b0000000 b0000000 0 00100000 + 01000000 0 00000000 b0100000 0 00100000>; clock-frequency = <1fca055>; interrupt-parent = <&mpic>; interrupts = <1b 2>; - interrupt-map-mask = <f800 0 0 7>; + interrupt-map-mask = <fb00 0 0 0>; interrupt-map = < - - // IDSEL 0x1a - d000 0 0 1 &i8259 6 2 - d000 0 0 2 &i8259 3 2 - d000 0 0 3 &i8259 4 2 - d000 0 0 4 &i8259 5 2 - - // IDSEL 0x1b - d800 0 0 1 &i8259 5 2 - d800 0 0 2 &i8259 0 0 - d800 0 0 3 &i8259 0 0 - d800 0 0 4 &i8259 0 0 - // IDSEL 0x1c USB - e000 0 0 1 &i8259 9 2 - e000 0 0 2 &i8259 a 2 - e000 0 0 3 &i8259 c 2 - e000 0 0 4 &i8259 7 2 + e000 0 0 0 &i8259 c 2 + e100 0 0 0 &i8259 9 2 + e200 0 0 0 &i8259 a 2 + e300 0 0 0 &i8259 b 2 // IDSEL 0x1d Audio - e800 0 0 1 &i8259 9 2 - e800 0 0 2 &i8259 a 2 - e800 0 0 3 &i8259 b 2 - e800 0 0 4 &i8259 0 0 + e800 0 0 0 &i8259 6 2 // IDSEL 0x1e Legacy - f000 0 0 1 &i8259 c 2 - f000 0 0 2 &i8259 0 0 - f000 0 0 3 &i8259 0 0 - f000 0 0 4 &i8259 0 0 + f000 0 0 0 &i8259 7 2 + f100 0 0 0 &i8259 7 2 // IDSEL 0x1f IDE/SATA - f800 0 0 1 &i8259 6 2 - f800 0 0 2 &i8259 0 0 - f800 0 0 3 &i8259 0 0 - f800 0 0 4 &i8259 0 0 + f800 0 0 0 &i8259 e 2 + f900 0 0 0 &i8259 5 2 >; uli1575@0 { reg = <0 0 0 0 0>; @@ -274,10 +264,10 @@ #address-cells = <3>; ranges = <02000000 0 b0000000 02000000 0 b0000000 - 0 10000000 + 0 00100000 01000000 0 00000000 01000000 0 00000000 - 0 00080000>; + 0 00100000>; pci_bridge@0 { reg = <0 0 0 0 0>; @@ -285,10 +275,10 @@ #address-cells = <3>; ranges = <02000000 0 b0000000 02000000 0 b0000000 - 0 20000000 + 0 00100000 01000000 0 00000000 01000000 0 00000000 - 0 00100000>; + 0 00100000>; isa@1e { device_type = "isa"; @@ -296,7 +286,8 @@ #size-cells = <1>; #address-cells = <2>; reg = <f000 0 0 0 0>; - ranges = <1 0 01000000 0 0 + ranges = <1 0 + 01000000 0 0 00001000>; interrupt-parent = <&i8259>; @@ -312,8 +303,7 @@ built-in; compatible = "chrp,iic"; interrupts = <9 2>; - interrupt-parent = - <&mpic>; + interrupt-parent = <&mpic>; }; i8042@60 { @@ -321,8 +311,7 @@ #address-cells = <1>; reg = <1 60 1 1 64 1>; interrupts = <1 3 c 3>; - interrupt-parent = - <&i8259>; + interrupt-parent = <&i8259>; keyboard@0 { reg = <0>; @@ -336,8 +325,7 @@ }; rtc@70 { - compatible = - "pnpPNP,b00"; + compatible = "pnpPNP,b00"; reg = <1 70 2>; }; |