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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-22 10:38:44 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-22 22:09:00 +0100 |
| commit | d04533650f64fe3367e180f3e488d92205152cd3 (patch) | |
| tree | 5f183668d97d9655a8517e61afd46bfa2f80b101 /arch/mips/sibyte/sb1250/smp.c | |
| parent | 06d428d719dece96c01532b62df4140f4e69a308 (diff) | |
| download | blackbird-op-linux-d04533650f64fe3367e180f3e488d92205152cd3.tar.gz blackbird-op-linux-d04533650f64fe3367e180f3e488d92205152cd3.zip | |
[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
The BCM148 has 4 cores but there are also just 4 generic timers available
so use the ZBbus cycle counter instead of it. In addition the ZBbus
counter also offers a much higher resolution and 64-bit counting so I'm
considering a later complete conversion to it once I figure out if all
members of the Sibyte SOC family support it - the docs seem to agree but
the headers files seem to disagree ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/sb1250/smp.c')
| -rw-r--r-- | arch/mips/sibyte/sb1250/smp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index aaa4f30dda79..3f52c95a4eb8 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -46,7 +46,7 @@ static void *mailbox_regs[] = { /* * SMP init and finish on secondary CPUs */ -void sb1250_smp_init(void) +void __cpuinit sb1250_smp_init(void) { unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | STATUSF_IP1 | STATUSF_IP0; @@ -55,7 +55,7 @@ void sb1250_smp_init(void) change_c0_status(ST0_IM, imask); } -void sb1250_smp_finish(void) +void __cpuinit sb1250_smp_finish(void) { extern void sb1250_clockevent_init(void); |
