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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-11-02 19:37:26 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-11-02 19:37:26 -0700 |
| commit | 29dd5a7733fcb72696e90247ffbab57b0a591f67 (patch) | |
| tree | aafbbdc38ea9f9ea42a594fc47b8bd37dc720c23 /arch/mips/sibyte/Kconfig | |
| parent | 71527bf8332ced9a961827272fe2f83fc5514f42 (diff) | |
| parent | 3be51f70e1f5e11a723d28b3dde26bc3aacdbc71 (diff) | |
| download | blackbird-op-linux-29dd5a7733fcb72696e90247ffbab57b0a591f67.tar.gz blackbird-op-linux-29dd5a7733fcb72696e90247ffbab57b0a591f67.zip | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (25 commits)
[MIPS] Jazz: disable PIT; cleanup R4030 clockevent
[MIPS] Bigsur supports highmem.
[MIPS] mtx-1: Enable -Werror.
[MIPS] mtx-1: Remove unused mtx1_sys_btn.
[MIPS] Pb1200: Enable -Werror.
[MIPS] Fix and cleanup the MIPS part of the (ab)use of CLOCK_TICK_RATE.
[MIPS] SNI: register a02r clockevent; don't use PIT timer
[MIPS] i8253.h: Remove all i8259 related definitions.
[MIPS] i8253: Cleanup.
[MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now.
[MIPS] Pb1200: Fix warning.
[MIPS] Pb1200: Fix warning.
[MIPS] IP27: Fix build error.
[MIPS] Excite: Fix build error.
[MIPS] Sibyte: Split and move clock code.
[MIPS] Sibyte: Fixes for oneshot timer mode.
[MIPS] Sibyte: Remove blank line.
[MIPS] Swarm: Fix build failure
[MIPS] time: Code cleanups
[MIPS] time: Remove now unused local_timer_interrupt.
...
Diffstat (limited to 'arch/mips/sibyte/Kconfig')
| -rw-r--r-- | arch/mips/sibyte/Kconfig | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index e8fb880272bd..366b19d33f77 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -1,5 +1,7 @@ config SIBYTE_SB1250 bool + select CEVT_SB1250 + select CSRC_SB1250 select HW_HAS_PCI select IRQ_CPU select SIBYTE_ENABLE_LDT_IF_PCI @@ -9,6 +11,8 @@ config SIBYTE_SB1250 config SIBYTE_BCM1120 bool + select CEVT_SB1250 + select CSRC_SB1250 select IRQ_CPU select SIBYTE_BCM112X select SIBYTE_HAS_ZBUS_PROFILING @@ -16,6 +20,8 @@ config SIBYTE_BCM1120 config SIBYTE_BCM1125 bool + select CEVT_SB1250 + select CSRC_SB1250 select HW_HAS_PCI select IRQ_CPU select SIBYTE_BCM112X @@ -24,6 +30,8 @@ config SIBYTE_BCM1125 config SIBYTE_BCM1125H bool + select CEVT_SB1250 + select CSRC_SB1250 select HW_HAS_PCI select IRQ_CPU select SIBYTE_BCM112X @@ -33,12 +41,16 @@ config SIBYTE_BCM1125H config SIBYTE_BCM112X bool + select CEVT_SB1250 + select CSRC_SB1250 select IRQ_CPU select SIBYTE_SB1xxx_SOC select SIBYTE_HAS_ZBUS_PROFILING config SIBYTE_BCM1x80 bool + select CEVT_BCM1480 + select CSRC_BCM1480 select HW_HAS_PCI select IRQ_CPU select SIBYTE_HAS_ZBUS_PROFILING @@ -47,6 +59,8 @@ config SIBYTE_BCM1x80 config SIBYTE_BCM1x55 bool + select CEVT_BCM1480 + select CSRC_BCM1480 select HW_HAS_PCI select IRQ_CPU select SIBYTE_SB1xxx_SOC |
