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authorJames Hogan <james.hogan@imgtec.com>2014-05-29 10:16:26 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2014-05-30 13:00:02 +0200
commitb5dfc6c10608fdf0c35a747a0a3bf3f6e40a38e1 (patch)
tree3b9722c836af500a362e73930dbf0f1b21685211 /arch/mips/kvm
parentfacaaec1a72db90127b71d22e788596cf1991ae1 (diff)
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MIPS: KVM: Use tlb_write_random
When MIPS KVM needs to write a TLB entry for the guest it reads the CP0_Random register, uses it to generate the CP_Index, and writes the TLB entry using the TLBWI instruction (tlb_write_indexed()). However there's an instruction for that, TLBWR (tlb_write_random()) so use that instead. This happens to also fix an issue with Ingenic XBurst cores where the same TLB entry is replaced each time preventing forward progress on stores due to alternating between TLB load misses for the instruction fetch and TLB store misses. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/mips/kvm')
-rw-r--r--arch/mips/kvm/kvm_tlb.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/mips/kvm/kvm_tlb.c b/arch/mips/kvm/kvm_tlb.c
index 50ab9c4d4a5d..9d371ee0a755 100644
--- a/arch/mips/kvm/kvm_tlb.c
+++ b/arch/mips/kvm/kvm_tlb.c
@@ -222,16 +222,14 @@ kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
return -1;
}
- if (idx < 0) {
- idx = read_c0_random() % current_cpu_data.tlbsize;
- write_c0_index(idx);
- mtc0_tlbw_hazard();
- }
write_c0_entrylo0(entrylo0);
write_c0_entrylo1(entrylo1);
mtc0_tlbw_hazard();
- tlb_write_indexed();
+ if (idx < 0)
+ tlb_write_random();
+ else
+ tlb_write_indexed();
tlbw_use_hazard();
#ifdef DEBUG
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