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| author | Ingo Molnar <mingo@elte.hu> | 2009-03-26 18:29:40 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-26 18:29:40 +0100 |
| commit | 5a54bd1307471c1cd0521402fe65e2057edcab2f (patch) | |
| tree | 25fb6a543db4ccc11b6d5662ed2e7facfce39ae7 /arch/mips/kernel/traps.c | |
| parent | f9f35677d81adb0feedcd6e0e661784805c8facd (diff) | |
| parent | 8e0ee43bc2c3e19db56a4adaa9a9b04ce885cd84 (diff) | |
| download | blackbird-op-linux-5a54bd1307471c1cd0521402fe65e2057edcab2f.tar.gz blackbird-op-linux-5a54bd1307471c1cd0521402fe65e2057edcab2f.zip | |
Merge commit 'v2.6.29' into core/header-fixes
Diffstat (limited to 'arch/mips/kernel/traps.c')
| -rw-r--r-- | arch/mips/kernel/traps.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f6083c6bfaa4..b2d7041341b8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -944,6 +944,9 @@ asmlinkage void do_mdmx(struct pt_regs *regs) force_sig(SIGILL, current); } +/* + * Called with interrupts disabled. + */ asmlinkage void do_watch(struct pt_regs *regs) { u32 cause; @@ -963,9 +966,12 @@ asmlinkage void do_watch(struct pt_regs *regs) */ if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { mips_read_watch_registers(); + local_irq_enable(); force_sig(SIGTRAP, current); - } else + } else { mips_clear_watch_registers(); + local_irq_enable(); + } } asmlinkage void do_mcheck(struct pt_regs *regs) @@ -1582,7 +1588,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size) static char panic_null_cerr[] __cpuinitdata = "Trying to set NULL cache error exception handler"; -/* Install uncached CPU exception handler */ +/* + * Install uncached CPU exception handler. + * This is suitable only for the cache error exception which is the only + * exception handler that is being run uncached. + */ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { @@ -1593,7 +1603,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long uncached_ebase = TO_UNCAC(ebase); #endif if (cpu_has_mips_r2) - ebase += (read_c0_ebase() & 0x3ffff000); + uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); |
