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| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-01-30 17:21:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-06 21:25:21 +0100 |
| commit | 02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e (patch) | |
| tree | 08224e4eb6d1b1471cc3322b626250e2d82bce7e /arch/mips/include | |
| parent | 0414855fdc4a40da05221fc6062cccbc0c30f169 (diff) | |
| download | blackbird-op-linux-02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e.tar.gz blackbird-op-linux-02dc6bfb080e8205aacea5c4b4dd6a9bd4c9406e.zip | |
MIPS: mm: c-r4k: Detect instruction cache aliases
The *Aptiv cores can use the CONF7/IAR bit to detect if the core
has hardware support to remove instruction cache aliasing.
This also defines the CONF7/AR bit in order to avoid using
the '16' magic number.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6499/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index bbc3dd4294bc..0c746176d31c 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -653,6 +653,9 @@ #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) +#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) +#define MIPS_CONF7_AR (_ULCAST_(1) << 16) + /* EntryHI bit definition */ #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) |
