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| author | John Crispin <blogic@openwrt.org> | 2012-11-09 13:43:30 +0100 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-11-11 18:47:35 +0100 |
| commit | af14a456c58c153c6d761e6c0af48157692b52ad (patch) | |
| tree | 15256dca6cca0566f6fa3ca766a7572c627cef97 /arch/mips/include/asm/mach-lantiq | |
| parent | f2bbe41c507b475c6f0ae1fca69c7aac6d31d228 (diff) | |
| download | blackbird-op-linux-af14a456c58c153c6d761e6c0af48157692b52ad.tar.gz blackbird-op-linux-af14a456c58c153c6d761e6c0af48157692b52ad.zip | |
MIPS: lantiq: adds code for booting GPHY
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to
boot them up.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4522
Diffstat (limited to 'arch/mips/include/asm/mach-lantiq')
| -rw-r--r-- | arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 6a2df709c576..133336b493b6 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase; #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) +/* allow booting xrx200 phys */ +int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr); + /* request a non-gpio and set the PIO config */ #define PMU_PPE BIT(13) extern void ltq_pmu_enable(unsigned int module); |
