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authorOskar Schirmer <oskar@linutronix.de>2011-02-17 16:42:58 +0100
committerThomas Gleixner <tglx@linutronix.de>2011-03-11 10:06:05 +0100
commit85922e54a3a14a6aee6c0b1fc67d81ef0c60fc9c (patch)
tree7ad5d37246e948424769c0456cd7d09f95f0192e /arch/microblaze/platform
parent30d913556b25db11f2537f4412487c6e81dc0374 (diff)
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arm: tcc8k: Choose PLL settings conforming to board layout
The evaluation board is driven with 1.2V core voltage, so system clock must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose appropriate values and set DTCMWAIT accordingly. Adapt UART setting to avoid console log interruption and wait for the specified locking time of 300us to pass. Signed-off-by: Oskar Schirmer <oskar@linutronix.de> Cc: bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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