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| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 13:35:55 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:18 +1000 |
| commit | 8ce877a8eb8293b5b2c07f259d694026b0f519e4 (patch) | |
| tree | d478523ee8bec4ecc638c9f9a35816fc12aaa37f /arch/m68k/include/asm/cacheflush_no.h | |
| parent | 3d461401eb5e3a8c471e92500aebd6c115273fba (diff) | |
| download | blackbird-op-linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.tar.gz blackbird-op-linux-8ce877a8eb8293b5b2c07f259d694026b0f519e4.zip | |
m68knommu: clean up ColdFire cache control code
The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.
The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.
I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/cacheflush_no.h')
| -rw-r--r-- | arch/m68k/include/asm/cacheflush_no.h | 40 |
1 files changed, 6 insertions, 34 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 52b11ac9a30c..8ada4ffc98e5 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -2,7 +2,7 @@ #define _M68KNOMMU_CACHEFLUSH_H /* - * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com> + * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com> */ #include <linux/mm.h> #include <asm/mcfsim.h> @@ -10,7 +10,7 @@ #define flush_cache_all() __flush_cache_all() #define flush_cache_mm(mm) do { } while (0) #define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) __flush_cache_all() +#define flush_cache_range(vma, start, end) do { } while (0) #define flush_cache_page(vma, vmaddr) do { } while (0) #ifndef flush_dcache_range #define flush_dcache_range(start,len) __flush_cache_all() @@ -33,41 +33,13 @@ #ifndef __flush_cache_all static inline void __flush_cache_all(void) { -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) +#ifdef CACHE_INVALIDATE __asm__ __volatile__ ( - "movel #0x81400110, %%d0\n\t" + "movel %0, %%d0\n\t" "movec %%d0, %%CACR\n\t" "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M523x || CONFIG_M527x */ -#if defined(CONFIG_M528x) - __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M528x */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) - __asm__ __volatile__ ( - "movel #0x81000100, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ -#ifdef CONFIG_M5249 - __asm__ __volatile__ ( - "movel #0xa1000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5249 */ -#ifdef CONFIG_M532x - __asm__ __volatile__ ( - "movel #0x81000210, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M532x */ + : : "i" (CACHE_INVALIDATE) : "d0" ); +#endif } #endif /* __flush_cache_all */ |
