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author | Graf Yang <graf.yang@analog.com> | 2009-05-06 09:59:11 +0000 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-12 06:11:26 -0400 |
commit | f5879fda09ea98d7aa845a0e0fa7e508452e5f9f (patch) | |
tree | b1404b8cbaa64758f0d1caac3349384e42e34057 /arch/blackfin/mach-bf561/include/mach/defBF561.h | |
parent | f339f46b05cfe289024b15a0525c8b61f1426a88 (diff) | |
download | blackbird-op-linux-f5879fda09ea98d7aa845a0e0fa7e508452e5f9f.tar.gz blackbird-op-linux-f5879fda09ea98d7aa845a0e0fa7e508452e5f9f.zip |
Blackfin: add MDMA defines to make cross-variant coding easier
Add some defines to make the BF538/BF561 look like most other Blackfin
parts in that it has a MDMA0 channel available for low level init.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/defBF561.h')
-rw-r--r-- | arch/blackfin/mach-bf561/include/mach/defBF561.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h index cf922295f4ce..5fc0f05026e0 100644 --- a/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -796,6 +796,62 @@ #define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */ #define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */ +#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR +#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR +#define MDMA_D0_CONFIG MDMA1_D0_CONFIG +#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT +#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY +#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT +#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY +#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR +#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR +#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS +#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP +#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT +#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT + +#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR +#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR +#define MDMA_S0_CONFIG MDMA1_S0_CONFIG +#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT +#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY +#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT +#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY +#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR +#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR +#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS +#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP +#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT +#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT + +#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR +#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR +#define MDMA_D1_CONFIG MDMA1_D1_CONFIG +#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT +#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY +#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT +#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY +#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR +#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR +#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS +#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP +#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT +#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT + +#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR +#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR +#define MDMA_S1_CONFIG MDMA1_S1_CONFIG +#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT +#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY +#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT +#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY +#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR +#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR +#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS +#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP +#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT +#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT + /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */ #define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */ #define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */ |