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| author | Graf Yang <graf.yang@analog.com> | 2009-05-07 04:09:15 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-06-12 06:11:41 -0400 |
| commit | 5ba766752d14a741aa2d7a3c321917a310b34afb (patch) | |
| tree | a97d8174cded42843de44b08d613c350b28a2729 /arch/blackfin/include/asm | |
| parent | a261eec0009b6093727fb7a59b12a10c6c981714 (diff) | |
| download | blackbird-op-linux-5ba766752d14a741aa2d7a3c321917a310b34afb.tar.gz blackbird-op-linux-5ba766752d14a741aa2d7a3c321917a310b34afb.zip | |
Blackfin: work around anomaly 05000220
When possible, work around anomaly 05000220 (external memory is write
back cached, but L2 is not cached). If not possible, detect the
conditions at build time and reject any qualifying configurations.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm')
| -rw-r--r-- | arch/blackfin/include/asm/cplb.h | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index ad566ff9ad16..a75a6a9f0949 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -53,29 +53,32 @@ #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) #endif +#define SDRAM_DNON_CHBL (CPLB_COMMON) +#define SDRAM_EBIU (CPLB_COMMON) +#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) + #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) #ifdef CONFIG_SMP -#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) -#define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) -#define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) +#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) +#define L2_IMEMORY (CPLB_COMMON) +#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) #else -#ifdef CONFIG_BFIN_L2_CACHEABLE -#define L2_IMEMORY (SDRAM_IGENERIC) -#define L2_DMEMORY (SDRAM_DGENERIC) -#else -#define L2_IMEMORY (CPLB_COMMON) -#define L2_DMEMORY (CPLB_COMMON) -#endif /* CONFIG_BFIN_L2_CACHEABLE */ - -#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) +#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) +#define L2_IMEMORY (SDRAM_IGENERIC) + +# if defined(CONFIG_BFIN_L2_WB) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) +# elif defined(CONFIG_BFIN_L2_WT) +# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) +# elif defined(CONFIG_BFIN_L2_NOT_CACHED) +# define L2_DMEMORY (CPLB_COMMON) +# else +# define L2_DMEMORY (0) +# endif #endif /* CONFIG_SMP */ -#define SDRAM_DNON_CHBL (CPLB_COMMON) -#define SDRAM_EBIU (CPLB_COMMON) -#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) - #define SIZE_1K 0x00000400 /* 1K */ #define SIZE_4K 0x00001000 /* 4K */ #define SIZE_1M 0x00100000 /* 1M */ |
