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| author | Andre Przywara <andre.przywara@arm.com> | 2014-11-14 15:54:10 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-11-25 15:56:21 +0000 |
| commit | 301bcfac42897dbd1b0b3c1be49f24654a1bc49e (patch) | |
| tree | bd42ce2fcf06bc99fb2b553969cdc2dba3cb1c0b /arch/arm64/mm/cache.S | |
| parent | e116a375423393cdb94714e90a96857005d58428 (diff) | |
| download | blackbird-op-linux-301bcfac42897dbd1b0b3c1be49f24654a1bc49e.tar.gz blackbird-op-linux-301bcfac42897dbd1b0b3c1be49f24654a1bc49e.zip | |
arm64: add Cortex-A53 cache errata workaround
The ARM errata 819472, 826319, 827319 and 824069 define the same
workaround for these hardware issues in certain Cortex-A53 parts.
Use the new alternatives framework and the CPU MIDR detection to
patch "cache clean" into "cache clean and invalidate" instructions if
an affected CPU is detected at runtime.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[will: add __maybe_unused to squash gcc warning]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/mm/cache.S')
| -rw-r--r-- | arch/arm64/mm/cache.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 23663837acff..8eaf18577d71 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -20,6 +20,8 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/cpufeature.h> +#include <asm/alternative-asm.h> #include "proc-macros.S" @@ -210,7 +212,7 @@ __dma_clean_range: dcache_line_size x2, x3 sub x3, x2, #1 bic x0, x0, x3 -1: dc cvac, x0 // clean D / U line +1: alternative_insn "dc cvac, x0", "dc civac, x0", ARM64_WORKAROUND_CLEAN_CACHE add x0, x0, x2 cmp x0, x1 b.lo 1b |
