diff options
author | Olof Johansson <olof@lixom.net> | 2018-06-02 01:30:07 -0700 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2018-06-02 01:30:07 -0700 |
commit | 171d429a1df9ea9deeab24bd623f14c8006da466 (patch) | |
tree | 24fef3db74f37abd9a73e2a8966ef5c10399564b /arch/arm64/boot/dts/renesas/r8a77980.dtsi | |
parent | ae709bf8ad8b83d8b6f6408953456662ab71a990 (diff) | |
parent | 908001d778eba06ee1d832863d4e9a1e2cfd4746 (diff) | |
download | blackbird-op-linux-171d429a1df9ea9deeab24bd623f14c8006da466.tar.gz blackbird-op-linux-171d429a1df9ea9deeab24bd623f14c8006da466.zip |
Merge tag 'renesas-arm64-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
Renesas ARM64 Based SoC DT Updates for v4.18
* Cleanups:
- Correct whitespace
- sort subnodes of the root and soc nodes
* R-Car M3-N (r8a77965) SoC
- Describe MSIOF SPI, PWM, SDHI and I2C devices in DT
- Add thermal support
* R-Car H3 (r8a7795) and R-Car M3-W (r8a7796) SoCs
- Decrease temperature hysteresis
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Add address properties to rcar_sound port nodes
* R-Car H3 (r8a7795), M3-W (r8a7796) V3M (r8a77970) and D3 (r8a77995) SoCs
- Enable IPMMU devices
* R-Car M3-N (r8a77965) and V3H (r8a77980) SoCs
- Use sysc binding macros
- Describe USB2 and USB3 devices in DT
* R-Car V3M (r8a77970) SoC
- Add SMP Support
- Correct IPMMU DS1 bit number
* R-Car V3H (r8a77980) SoC
- Use CPG clock binding macros
* R-Car V3H (r8a77980) and V3M (r8a77970) SoCs
- Disable EtherAVB
* R-Car D3 (r8a77995) SoC
- Describe VIN4 in DT
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support
* Salvator-XS boards with R-Car H3 (r8a7795) SoC
- Enable USB2.0 channel 3
* Salvator-X and Salvator-XS boards with M3-N (r8a77965) SoC
- Enable DU
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Enable nable VIN, CSI-2 and ADV7482
- Add PMIC DDR Backup Power config
- Add EEPROM
- Enable HDMI Sound
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs, and
Draak board with R-Car D3 (r8a77995) SoC
- Consistently name EtherAVB mdio pin group
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support: Memory, Main crystal, Serial console
- Enable Ethernet
- Revise PSCI node
- Revise cache controller node
* V3HSK board with R-Car V3H (r8a77980) SoC
- Initial board device tree
- Enable PFC support and use for EtherAVB
* V3MSK board with R-Car V3M (r8a77970) SoC
- Add DU/LVDS/HDMI support
- Enable PFC for EtherAVB
* Condor board with R-Car V3H (r8a77980) SoC
- Enable eMMC
- Enable PFC support and use for EtherAVB and SCIF0
* Eagle board with R-Car V3M (r8a77970) SoC
- Enable HDMI output
* Eagle board with R-Car V3M (r8a77970) SoC and
Condor board with R-Car V3H (r8a77980) SoC
- Enable CAN-FD
* tag 'renesas-arm64-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (102 commits)
arm64: dts: renesas: salvator-common: Add ADV7482 support
arm64: dts: renesas: salvator-common: enable VIN
arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7795-es1: add CSI-2 node
arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add I2C support
arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB
arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
arm64: dts: renesas: r8a77990: Add GPIO device nodes
arm64: dts: renesas: r8a77990: Add PFC device node
arm64: dts: renesas: initial V3HSK board device tree
arm64: dts: renesas: r8a77980: disable EtherAVB
arm64: dts: renesas: r8a77970: disable EtherAVB
arm64: dts: renesas: r8a77995: Add VIN4
arm64: dts: renesas: r8a77980: add resets property to CAN-FD node
arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
arm64: dts: renesas: r8a77965: Add SDHI device nodes
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a77980.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77980.dtsi | 99 |
1 files changed, 75 insertions, 24 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 03845fd74996..4c40f9f0ebc9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -6,9 +6,10 @@ * Copyright (C) 2018 Cogent Embedded, Inc. */ +#include <dt-bindings/clock/r8a77980-cpg-mssr.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/power/r8a77980-sysc.h> / { compatible = "renesas,r8a77980"; @@ -23,20 +24,27 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0>; - clocks = <&cpg CPG_CORE 0>; - power-domains = <&sysc 5>; + clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; + power-domains = <&sysc R8A77980_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; L2_CA53: cache-controller { compatible = "cache"; - power-domains = <&sysc 21>; + power-domains = <&sysc R8A77980_PD_CA53_SCU>; cache-unified; cache-level = <2>; }; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -71,6 +79,11 @@ #size-cells = <2>; ranges; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77980"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77980-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -99,13 +112,13 @@ reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x31>, <&dmac1 0x30>, <&dmac2 0x31>, <&dmac2 0x30>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 520>; status = "disabled"; }; @@ -117,13 +130,13 @@ reg = <0 0xe6550000 0 0x60>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 519>; status = "disabled"; }; @@ -135,13 +148,13 @@ reg = <0 0xe6560000 0 0x60>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x35>, <&dmac1 0x34>, <&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 518>; status = "disabled"; }; @@ -153,17 +166,42 @@ reg = <0 0xe66a0000 0 0x60>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x37>, <&dmac1 0x36>, <&dmac2 0x37>, <&dmac2 0x36>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 517>; status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77980-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77980_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77980", "renesas,etheravb-rcar-gen3"; @@ -201,11 +239,12 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; scif0: serial@e6e60000 { @@ -215,13 +254,13 @@ reg = <0 0xe6e60000 0 0x40>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 207>; status = "disabled"; }; @@ -233,13 +272,13 @@ reg = <0 0xe6e68000 0 0x40>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 206>; status = "disabled"; }; @@ -251,13 +290,13 @@ reg = <0 0xe6c50000 0 0x40>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x57>, <&dmac1 0x56>, <&dmac2 0x57>, <&dmac2 0x56>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 204>; status = "disabled"; }; @@ -269,13 +308,13 @@ reg = <0 0xe6c40000 0 0x40>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 19>, + <&cpg CPG_CORE R8A77980_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x59>, <&dmac1 0x58>, <&dmac2 0x59>, <&dmac2 0x58>; dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 203>; status = "disabled"; }; @@ -308,7 +347,7 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; @@ -342,12 +381,24 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; }; + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a77980", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 314>; + max-frequency = <200000000>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -361,7 +412,7 @@ IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 408>; }; |