diff options
| author | Thomas Abraham <thomas.abraham@linaro.org> | 2011-10-24 11:47:57 +0200 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-12-23 10:06:58 +0900 |
| commit | c3310fbbeb9db6967900ed22eb3d0bd0bb0e892c (patch) | |
| tree | 0aaf7a11e30ab18ad39804f4fd8beac29d671d9b /arch/arm/plat-samsung/include/plat | |
| parent | afba7f91e64025748a2cfec181e5a910fd0dee0e (diff) | |
| download | blackbird-op-linux-c3310fbbeb9db6967900ed22eb3d0bd0bb0e892c.tar.gz blackbird-op-linux-c3310fbbeb9db6967900ed22eb3d0bd0bb0e892c.zip | |
serial: samsung: remove all uses of get_clksrc and set_clksrc
With clkdev based clock lookup support, the clock set and get operation
using clock names communicated between the samsung uart driver and the
SoC specific extension can be removed.
In addition to that, for each platform specific extension, add the
default clock selection, number of clock options for uart baud generator,
clock selection bit mask and shift values which is required by the
clkdev support in samsung uart driver.
The default clock selection value 'def_clk_sel' specifies the default clock
to be used as the source clock for baud rate generator in case the platform
code does not specify the same.
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung/include/plat')
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-serial.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h index 25f0c364f61a..133fa97fbc82 100644 --- a/arch/arm/plat-samsung/include/plat/regs-serial.h +++ b/arch/arm/plat-samsung/include/plat/regs-serial.h @@ -71,6 +71,7 @@ #define S3C2410_LCON_IRM (1<<6) #define S3C2440_UCON_CLKMASK (3<<10) +#define S3C2440_UCON_CLKSHIFT (10) #define S3C2440_UCON_PCLK (0<<10) #define S3C2440_UCON_UCLK (1<<10) #define S3C2440_UCON_PCLK2 (2<<10) @@ -78,6 +79,7 @@ #define S3C2443_UCON_EPLL (3<<10) #define S3C6400_UCON_CLKMASK (3<<10) +#define S3C6400_UCON_CLKSHIFT (10) #define S3C6400_UCON_PCLK (0<<10) #define S3C6400_UCON_PCLK2 (2<<10) #define S3C6400_UCON_UCLK0 (1<<10) @@ -90,11 +92,14 @@ #define S3C2440_UCON_DIVSHIFT (12) #define S3C2412_UCON_CLKMASK (3<<10) +#define S3C2412_UCON_CLKSHIFT (10) #define S3C2412_UCON_UCLK (1<<10) #define S3C2412_UCON_USYSCLK (3<<10) #define S3C2412_UCON_PCLK (0<<10) #define S3C2412_UCON_PCLK2 (2<<10) +#define S3C2410_UCON_CLKMASK (1 << 10) +#define S3C2410_UCON_CLKSHIFT (10) #define S3C2410_UCON_UCLK (1<<10) #define S3C2410_UCON_SBREAK (1<<4) @@ -193,6 +198,7 @@ /* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) +#define S5PV210_UCON_CLKSHIFT (10) #define S5PV210_UCON_PCLK (0<<10) #define S5PV210_UCON_UCLK (1<<10) @@ -221,7 +227,6 @@ #define S5PV210_UFSTAT_RXMASK (255<<0) #define S5PV210_UFSTAT_RXSHIFT (0) -#define NO_NEED_CHECK_CLKSRC 1 #define S3C2410_UCON_CLKSEL0 (1 << 0) #define S3C2410_UCON_CLKSEL1 (1 << 1) #define S3C2410_UCON_CLKSEL2 (1 << 2) |
