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| author | Ben Dooks <ben@simtec.co.uk> | 2009-08-03 17:26:50 +0100 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2009-08-14 01:26:09 +0100 |
| commit | a2c195fdde20772a90ee98ce3523dcfbda49eee6 (patch) | |
| tree | 9c54f3bb7083095688dee32ead4ec2c5bdf32896 /arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c | |
| parent | d91e9a7ab93e09e5a0fbed73f3a6a330f14620a4 (diff) | |
| download | blackbird-op-linux-a2c195fdde20772a90ee98ce3523dcfbda49eee6.tar.gz blackbird-op-linux-a2c195fdde20772a90ee98ce3523dcfbda49eee6.zip | |
ARM: S3C24XX: Add SPI bus 1 on GPD8 through GPD10
Add configuration callback for SPI bus 1 on GPD[8..10] and ensure the
correct GPIO configuration register definitions in regs-gpio.h
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c')
| -rw-r--r-- | arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c new file mode 100644 index 000000000000..89fcf5308cf6 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c @@ -0,0 +1,38 @@ +/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c + * + * Copyright (c) 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> + +#include <mach/spi.h> +#include <mach/regs-gpio.h> + +void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi, + int enable) +{ + + printk(KERN_INFO "%s(%d)\n", __func__, enable); + if (enable) { + s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1); + s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1); + s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1); + s3c2410_gpio_pullup(S3C2410_GPD(10), 0); + s3c2410_gpio_pullup(S3C2410_GPD(9), 0); + } else { + s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT); + s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT); + s3c2410_gpio_pullup(S3C2410_GPD(10), 1); + s3c2410_gpio_pullup(S3C2410_GPD(9), 1); + s3c2410_gpio_pullup(S3C2410_GPD(8), 1); + } +} |
