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| author | Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> | 2011-12-01 22:16:26 +0100 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2011-12-08 18:02:25 -0800 |
| commit | f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03 (patch) | |
| tree | e5174f71bffc3b93d4043a2e65756ff9ac85769d /arch/arm/plat-omap | |
| parent | 24ce2705c2dd50e51f325c6e57dec378adc8c135 (diff) | |
| download | blackbird-op-linux-f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03.tar.gz blackbird-op-linux-f9e5908fa04e15a681dc4695b53c2c0c1d9b9a03.zip | |
ARM: OMAP1: Update dpll1 default rate reprogramming method
According to comments in omap1_select_table_rate(), reprogramming dpll1
is tricky, and should always be done from SRAM.
While being at it, move OMAP730 special case handling inside
omap_sram_reprogram_clock().
Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1
reprogramming related issues", which it depends on.
Tested on Amstrad Delta.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap')
| -rw-r--r-- | arch/arm/plat-omap/sram.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 574351902c83..6b058a621e8d 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -222,6 +222,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { BUG_ON(!_omap_sram_reprogram_clock); + /* On 730, bit 13 must always be 1 */ + if (cpu_is_omap7xx()) + ckctl |= 0x2000; _omap_sram_reprogram_clock(dpllctl, ckctl); } |
