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authorAndrew Lunn <andrew@lunn.ch>2014-02-22 20:14:52 +0100
committerJason Cooper <jason@lakedaemon.net>2014-02-22 20:43:49 +0000
commit4b8f7a11c9fb680895e5079788653a59d6bdde16 (patch)
treed20f78bd55eb043f8f9e1be5e702301263b73079 /arch/arm/plat-iop
parent3c317d00ba4a9489c161857a574432c61fde4a2a (diff)
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ARM: MM: Add DT binding for Feroceon L2 cache
Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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