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| author | Vladimir Murzin <vladimir.murzin@arm.com> | 2016-08-30 17:30:02 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-09-06 15:51:07 +0100 |
| commit | 9a1af5f2206bd303ed201c6895c42ac3ac120a20 (patch) | |
| tree | f59e498b9d06d08ca811697b28d2034d0bd65ce7 /arch/arm/mm/proc-macros.S | |
| parent | b2bf482a5099264fb75936b5b552cdf3c247c93a (diff) | |
| download | blackbird-op-linux-9a1af5f2206bd303ed201c6895c42ac3ac120a20.tar.gz blackbird-op-linux-9a1af5f2206bd303ed201c6895c42ac3ac120a20.zip | |
ARM: 8606/1: V7M: introduce cache operations
This commit implements the cache operation for V7M.
It is based on V7 counterpart and differs as follows:
- cache operations are memory mapped
- only Thumb instruction set is supported
- we don't handle user access faults
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index c671f345266a..0d40c285bd86 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -7,6 +7,10 @@ #include <asm/asm-offsets.h> #include <asm/thread_info.h> +#ifdef CONFIG_CPU_V7M +#include <asm/v7m.h> +#endif + /* * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) */ @@ -70,7 +74,13 @@ * on ARMv7. */ .macro dcache_line_size, reg, tmp +#ifdef CONFIG_CPU_V7M + movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR + movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR + ldr \tmp, [\tmp] +#else mrc p15, 0, \tmp, c0, c0, 1 @ read ctr +#endif lsr \tmp, \tmp, #16 and \tmp, \tmp, #0xf @ cache line size encoding mov \reg, #4 @ bytes per word @@ -82,7 +92,13 @@ * on ARMv7. */ .macro icache_line_size, reg, tmp +#ifdef CONFIG_CPU_V7M + movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR + movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR + ldr \tmp, [\tmp] +#else mrc p15, 0, \tmp, c0, c0, 1 @ read ctr +#endif and \tmp, \tmp, #0xf @ cache line size encoding mov \reg, #4 @ bytes per word mov \reg, \reg, lsl \tmp @ actual cache line size |
