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author | Rob Herring <rob.herring@calxeda.com> | 2013-03-13 17:07:44 -0500 |
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committer | Rob Herring <rob.herring@calxeda.com> | 2013-04-11 15:11:21 -0500 |
commit | 818270d573674188cfe731992e66455e2e183e64 (patch) | |
tree | 0e3efbda0d8dd2c40b4dd1945878d0be4df57524 /arch/arm/mach-versatile/core.c | |
parent | cc8e9ad88487004372cae87718ff593d0a2fdc3a (diff) | |
download | blackbird-op-linux-818270d573674188cfe731992e66455e2e183e64.tar.gz blackbird-op-linux-818270d573674188cfe731992e66455e2e183e64.zip |
ARM: versatile: use OF init for sp804 timer
Enable DT based init for the sp804 timers on versatile DT platform.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Diffstat (limited to 'arch/arm/mach-versatile/core.c')
-rw-r--r-- | arch/arm/mach-versatile/core.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 25160aeaa3b7..54bb80b012ac 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd) /* Early initializations */ void __init versatile_init_early(void) { + u32 val; void __iomem *sys = __io_address(VERSATILE_SYS_BASE); osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000); + + /* + * set clock frequency: + * VERSATILE_REFCLK is 32KHz + * VERSATILE_TIMCLK is 1MHz + */ + val = readl(__io_address(VERSATILE_SCTL_BASE)); + writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, + __io_address(VERSATILE_SCTL_BASE)); } void __init versatile_init(void) @@ -785,19 +798,6 @@ void __init versatile_init(void) */ void __init versatile_timer_init(void) { - u32 val; - - /* - * set clock frequency: - * VERSATILE_REFCLK is 32KHz - * VERSATILE_TIMCLK is 1MHz - */ - val = readl(__io_address(VERSATILE_SCTL_BASE)); - writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, - __io_address(VERSATILE_SCTL_BASE)); /* * Initialise to a known state (all timers off) |