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authorJoonyoung Shim <jy0922.shim@samsung.com>2012-03-07 04:23:47 -0800
committerKukjin Kim <kgene.kim@samsung.com>2012-03-09 07:31:30 -0800
commit99f6e1f50cbb048325c966f2d0e7fe3e47010905 (patch)
treeb7e108793beb7d40685607a918e15aa2656cd5d0 /arch/arm/mach-s3c64xx/setup-usb-phy.c
parent6cdeddcc8149672d4b888709d063825a80304d09 (diff)
downloadblackbird-op-linux-99f6e1f50cbb048325c966f2d0e7fe3e47010905.tar.gz
blackbird-op-linux-99f6e1f50cbb048325c966f2d0e7fe3e47010905.zip
ARM: S3C64XX: Add usb otg phy control
This patch supports to control usb otg phy of S3C64XX. Currently, the driver for usb otg controls usb otg phy but it can be removed by this patch. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [Rebased on the newest git/kgene/linux-samsung #for-next] Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Mark Brown<broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/setup-usb-phy.c')
-rw-r--r--arch/arm/mach-s3c64xx/setup-usb-phy.c90
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
new file mode 100644
index 000000000000..f6757e02d7db
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/usb-phy.h>
+
+static int s3c_usb_otgphy_init(struct platform_device *pdev)
+{
+ struct clk *xusbxti;
+ u32 phyclk;
+
+ writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+ /* set clock frequency for PLL */
+ phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
+
+ xusbxti = clk_get(&pdev->dev, "xusbxti");
+ if (xusbxti && !IS_ERR(xusbxti)) {
+ switch (clk_get_rate(xusbxti)) {
+ case 12 * MHZ:
+ phyclk |= S3C_PHYCLK_CLKSEL_12M;
+ break;
+ case 24 * MHZ:
+ phyclk |= S3C_PHYCLK_CLKSEL_24M;
+ break;
+ default:
+ case 48 * MHZ:
+ /* default reference clock */
+ break;
+ }
+ clk_put(xusbxti);
+ }
+
+ /* TODO: select external clock/oscillator */
+ writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
+
+ /* set to normal OTG PHY */
+ writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
+ mdelay(1);
+
+ /* reset OTG PHY and Link */
+ writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
+ S3C_RSTCON);
+ udelay(20); /* at-least 10uS */
+ writel(0, S3C_RSTCON);
+
+ return 0;
+}
+
+static int s3c_usb_otgphy_exit(struct platform_device *pdev)
+{
+ writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
+ S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
+
+ writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+ return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+ if (type == S5P_USB_PHY_DEVICE)
+ return s3c_usb_otgphy_init(pdev);
+
+ return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+ if (type == S5P_USB_PHY_DEVICE)
+ return s3c_usb_otgphy_exit(pdev);
+
+ return -EINVAL;
+}
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