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author | Abhilash Kesavan <a.kesavan@samsung.com> | 2010-06-08 16:55:45 +0900 |
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committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-05 18:32:50 +0900 |
commit | 0ab0b6d226caa4a0268ecbce76a7376c3f40ee6b (patch) | |
tree | 729f66aa696b663b92e04d606eb1686b0f353307 /arch/arm/mach-s3c64xx/setup-ide.c | |
parent | db90005b5bdb7195b55e295548d7a7eb2014d94c (diff) | |
download | blackbird-op-linux-0ab0b6d226caa4a0268ecbce76a7376c3f40ee6b.tar.gz blackbird-op-linux-0ab0b6d226caa4a0268ecbce76a7376c3f40ee6b.zip |
ARM: S3C64XX: Add support for Compact Flash driver on SMDK6410
Following is added for the CF-ATA driver:
- Platform data strucure instantiation
- Platform device enabling code
- Addition of cfcon clock
- Platform-specific gpio setup code
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/setup-ide.c')
-rw-r--r-- | arch/arm/mach-s3c64xx/setup-ide.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c new file mode 100644 index 000000000000..c12c315f33bc --- /dev/null +++ b/arch/arm/mach-s3c64xx/setup-ide.c @@ -0,0 +1,46 @@ +/* linux/arch/arm/mach-s3c64xx/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S3C64XX setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <plat/gpio-cfg.h> + +void s3c64xx_ide_setup_gpio(void) +{ + u32 reg; + u32 gpio = 0; + + reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); + + /* Independent CF interface, CF chip select configuration */ + writel(reg | MEM_SYS_CFG_INDEP_CF | + MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG); + + s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4)); + + /* Set XhiDATA[15:0] pins as CF Data[15:0] */ + for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5)); + + /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */ + for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6)); + + /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ + s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1)); + for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++) + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6)); +} |