Merge branch 'next/cleanup-header' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup

From Kukjin Kim:
AS I commented, this makes <mach/*.h> local so that they could be removed.

* 'next/cleanup-header' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (26 commits)
  ARM: S3C64XX: Fix missing header error with CONFIG_CPU_IDLE enabled
  ARM: S3C64XX: make regs-syscon-power.h local
  ARM: S3C64XX: make regs-sys.h local
  ARM: S3C64XX: make regs-srom.h local
  ARM: S3C64XX: make regs-modem.h local
  ARM: S3C64XX: make regs-gpio-memport.h local
  ARM: S3C64XX: make crag6410.h local
  ARM: S3C24XX: remove dsc.c and make regs-dsc.h local
  ARM: S3C24XX: remove idle.h
  ARM: S3C2412: cleanup regs-s3c2412.h
  ARM: S3C2416: remove regs-s3c2416-mem.h and regs-s3c2416.h
  ARM: S3C24XX: make vr1000-cpld.h, vr1000-irq.h and vr1000-map.h local
  ARM: S3C24XX: make otom-map.h local
  ARM: S3C24XX: make osiris-cpld.h and osiris-map.h local
  ARM: S3C24XX: make h1940.h and h1940-latch.h local
  ARM: S3C24XX: make gta02.h local
  ARM: S3C24XX: make bast-cpld.h, bast-irq.h and bast-map.h local
  ARM: S3C24XX: make anubis-cpld, anubis-irq and anubis-map local
  ARM: SAMSUNG: cleanup mach/gpio-fns.h gpio-track.h and gpio-nrs.h
  ARM: SAMSUNG: cleanup mach/regs-audss.h file
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 58 insertions, 0 deletions

diff --git a/arch/arm/mach-s3c64xx/regs-srom.h b/arch/arm/mach-s3c64xx/regs-srom.h
new file mode 100644
index 000000000000..d56f3386eb00
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/regs-srom.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2009 Andy Green <andy@warmcat.com>
+ *
+ * S3C64XX SROM definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_S3C64XX_REGS_SROM_H
+#define __MACH_S3C64XX_REGS_SROM_H __FILE__
+
+#define S3C64XX_SROMREG(x)	(S3C_VA_MEM + (x))
+
+#define S3C64XX_SROM_BW		S3C64XX_SROMREG(0)
+#define S3C64XX_SROM_BC0	S3C64XX_SROMREG(4)
+#define S3C64XX_SROM_BC1	S3C64XX_SROMREG(8)
+#define S3C64XX_SROM_BC2	S3C64XX_SROMREG(0xc)
+#define S3C64XX_SROM_BC3	S3C64XX_SROMREG(0x10)
+#define S3C64XX_SROM_BC4	S3C64XX_SROMREG(0x14)
+#define S3C64XX_SROM_BC5	S3C64XX_SROMREG(0x18)
+
+/*
+ * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
+ */
+
+#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT	0
+#define S3C64XX_SROM_BW__WAITENABLE__SHIFT	2
+#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT	3
+#define S3C64XX_SROM_BW__CS_MASK		0xf
+
+#define S3C64XX_SROM_BW__NCS0__SHIFT	0
+#define S3C64XX_SROM_BW__NCS1__SHIFT	4
+#define S3C64XX_SROM_BW__NCS2__SHIFT	8
+#define S3C64XX_SROM_BW__NCS3__SHIFT	0xc
+#define S3C64XX_SROM_BW__NCS4__SHIFT	0x10
+
+/*
+ * applies to same to BCS0 - BCS4
+ */
+
+#define S3C64XX_SROM_BCX__PMC__SHIFT	0
+#define S3C64XX_SROM_BCX__PMC__MASK	3
+#define S3C64XX_SROM_BCX__TACP__SHIFT	4
+#define S3C64XX_SROM_BCX__TACP__MASK	0xf
+#define S3C64XX_SROM_BCX__TCAH__SHIFT	8
+#define S3C64XX_SROM_BCX__TCAH__MASK	0xf
+#define S3C64XX_SROM_BCX__TCOH__SHIFT	12
+#define S3C64XX_SROM_BCX__TCOH__MASK	0xf
+#define S3C64XX_SROM_BCX__TACC__SHIFT	16
+#define S3C64XX_SROM_BCX__TACC__MASK	0x1f
+#define S3C64XX_SROM_BCX__TCOS__SHIFT	24
+#define S3C64XX_SROM_BCX__TCOS__MASK	0xf
+#define S3C64XX_SROM_BCX__TACS__SHIFT	28
+#define S3C64XX_SROM_BCX__TACS__MASK	0xf
+
+#endif /* __MACH_S3C64XX_REGS_SROM_H */