Orion: make PCIe/PCI support use mbus DRAM info

Make the Orion PCIe/PCI code initialise MBUS decode windows based on
mbus_dram_target_info instead of reading the info from the Orion DDR
unit decode registers directly, and move the window code with the other
PCI code, where it can be called as part of the generic PCIe/PCI init
process.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

1 files changed, 0 insertions, 148 deletions

diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
index ab4484cc14b7..69cd0876f6b9 100644
--- a/arch/arm/mach-orion/addr-map.c
+++ b/arch/arm/mach-orion/addr-map.c
@@ -93,56 +93,6 @@
 #define CPU_WIN_DEV_CS2		7
 
 /*
- * PCIE Address Decode Windows registers
- */
-#define PCIE_BAR_CTRL(n)	ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
-#define PCIE_BAR_LO(n)		ORION_PCIE_REG(0x0010 + ((n) * 8))
-#define PCIE_BAR_HI(n)		ORION_PCIE_REG(0x0014 + ((n) * 8))
-#define PCIE_WIN_CTRL(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
-					ORION_PCIE_REG(0x1880))
-#define PCIE_WIN_BASE(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
-					ORION_PCIE_REG(0x1884))
-#define PCIE_WIN_REMAP(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x182c + ((n) << 4)) : \
-					ORION_PCIE_REG(0x188c))
-#define PCIE_DEFWIN_CTRL	ORION_PCIE_REG(0x18b0)
-#define PCIE_EXPROM_WIN_CTRL	ORION_PCIE_REG(0x18c0)
-#define PCIE_EXPROM_WIN_REMP	ORION_PCIE_REG(0x18c4)
-#define PCIE_MAX_BARS		3
-#define PCIE_MAX_WINS		6
-
-/*
- * Use PCIE BAR '1' for all DDR banks
- */
-#define PCIE_DRAM_BAR		1
-
-/*
- * PCI Address Decode Windows registers
- */
-#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
-				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
-				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
-				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) : \
-				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
-				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
-				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
-#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
-#define PCI_CTRL_BASE_LO(n)	ORION_PCI_REG(0x1e00 | ((n) << 4))
-#define PCI_CTRL_BASE_HI(n)	ORION_PCI_REG(0x1e04 | ((n) << 4))
-#define PCI_CTRL_SIZE(n)	ORION_PCI_REG(0x1e08 | ((n) << 4))
-#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)
-
-/*
- * PCI configuration heleprs for BAR settings
- */
-#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
-#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
-#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
-
-/*
  * Gigabit Ethernet Address Decode Windows registers
  */
 #define ETH_WIN_BASE(win)	ORION_ETH_REG(0x200 + ((win) * 8))
@@ -312,104 +262,6 @@ void __init orion_setup_cpu_wins(void)
 	orion_mbus_dram_info.num_cs = cs;
 }
 
-/*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
- * WIN[0-3] -> DRAM bank[0-3]
- */
-void __init orion_setup_pcie_wins(void)
-{
-	u32 base, size, i;
-
-	/*
-	 * First, disable and clear BARs and windows
-	 */
-	for (i = 1; i < PCIE_MAX_BARS; i++) {
-		orion_write(PCIE_BAR_CTRL(i), 0);
-		orion_write(PCIE_BAR_LO(i), 0);
-		orion_write(PCIE_BAR_HI(i), 0);
-	}
-
-	for (i = 0; i < PCIE_MAX_WINS; i++) {
-		orion_write(PCIE_WIN_CTRL(i), 0);
-		orion_write(PCIE_WIN_BASE(i), 0);
-		orion_write(PCIE_WIN_REMAP(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks. Count total DDR size on the fly.
-	 */
-	base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
-	size = 0;
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 bank_base, bank_size;
-		bank_size = orion_read(DDR_SIZE_CS(i));
-		bank_base = orion_read(DDR_BASE_CS(i));
-		if (bank_size & DDR_BANK_EN) {
-			bank_size = DDR_REG_TO_SIZE(bank_size);
-			bank_base = DDR_REG_TO_BASE(bank_base);
-			orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
-			orion_write(PCIE_WIN_REMAP(i), 0);
-			orion_write(PCIE_WIN_CTRL(i),
-					((bank_size-1) & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					(TARGET_DDR << 4) |
-					(PCIE_DRAM_BAR << 1) | WIN_EN);
-			size += bank_size;
-		}
-	}
-
-	/*
-	 * Setup BAR[1] to all DRAM banks
-	 */
-	orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
-	orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
-	orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
-				((size - 1) & 0xffff0000) | WIN_EN);
-}
-
-void __init orion_setup_pci_wins(void)
-{
-	u32 base, size, i;
-
-	/*
-	 * First, disable windows
-	 */
-	orion_write(PCI_BAR_ENABLE, 0xffffffff);
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		base = orion_read(DDR_BASE_CS(i));
-		size = orion_read(DDR_SIZE_CS(i));
-		if (size & DDR_BANK_EN) {
-			u32 bus, dev, func, reg, val;
-			size = DDR_REG_TO_SIZE(size);
-			base = DDR_REG_TO_BASE(base);
-			bus = orion_pci_local_bus_nr();
-			dev = orion_pci_local_dev_nr();
-			func = PCI_CONF_FUNC_BAR_CS(i);
-			reg = PCI_CONF_REG_BAR_LO_CS(i);
-			orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
-			orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
-					(base & 0xfffff000) | (val & 0xfff));
-			reg = PCI_CONF_REG_BAR_HI_CS(i);
-			orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
-			orion_write(PCI_BAR_SIZE_DDR_CS(i),
-					(size - 1) & 0xfffff000);
-			orion_write(PCI_BAR_REMAP_DDR_CS(i),
-					base & 0xfffff000);
-			orion_clrbits(PCI_BAR_ENABLE, (1 << i));
-		}
-	}
-
-	/*
-	 * Disable automatic update of address remaping when writing to BARs
-	 */
-	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
-}
-
 void __init orion_setup_usb_wins(void)
 {
 	int i;