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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2014-04-30 14:39:37 +0300
committerTero Kristo <t-kristo@ti.com>2014-06-06 20:33:34 +0300
commit81c7e03acbcb68274be770134f8f04f270ffa859 (patch)
treeca6115715324f00441d89cc4a08e6a6382b48687 /arch/arm/mach-omap2
parent9ac33b0ce81fa48dd39e7ddfc1bf4519052181dd (diff)
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CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
In order to get correct clock dividers for AESS/ABE we need to set the dpll_abe_m2x2_ck rate to be double of dpll_abe_ck. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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