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author | Kalle Jokiniemi <kalle.jokiniemi@digia.com> | 2009-05-13 13:32:11 +0300 |
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committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-11-11 14:42:26 -0800 |
commit | 8a917d2fc80b7c45ce0146ff134168646274a9bd (patch) | |
tree | 5416b17c7d70203a870990f95f9c37646c6bdd9f /arch/arm/mach-omap2/sdrc.c | |
parent | ba50ea7eb9ce663511013b35608cf0753c9ab674 (diff) | |
download | blackbird-op-linux-8a917d2fc80b7c45ce0146ff134168646274a9bd.tar.gz blackbird-op-linux-8a917d2fc80b7c45ce0146ff134168646274a9bd.zip |
ARM: OMAP: SMS: save/restore of SMS_SYSCONFIG for off-mode
The SMS_SYSCONFIG register gets reset in off mode, added a
save/restore mechanism for that.
Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/sdrc.c')
-rw-r--r-- | arch/arm/mach-omap2/sdrc.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 07000de48f34..9a592199321c 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -37,12 +37,38 @@ static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; void __iomem *omap2_sdrc_base; void __iomem *omap2_sms_base; +struct omap2_sms_regs { + u32 sms_sysconfig; +}; + +static struct omap2_sms_regs sms_context; + /* SDRC_POWER register bits */ #define SDRC_POWER_EXTCLKDIS_SHIFT 3 #define SDRC_POWER_PWDENA_SHIFT 2 #define SDRC_POWER_PAGEPOLICY_SHIFT 0 /** + * omap2_sms_save_context - Save SMS registers + * + * Save SMS registers that need to be restored after off mode. + */ +void omap2_sms_save_context(void) +{ + sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG); +} + +/** + * omap2_sms_restore_context - Restore SMS registers + * + * Restore SMS registers that need to be Restored after off mode. + */ +void omap2_sms_restore_context(void) +{ + sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG); +} + +/** * omap2_sdrc_get_params - return SDRC register values for a given clock rate * @r: SDRC clock rate (in Hz) * @sdrc_cs0: chip select 0 ram timings ** @@ -132,4 +158,5 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); sdrc_write_reg(l, SDRC_POWER); + omap2_sms_save_context(); } |