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author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2012-09-05 10:22:45 -0400 |
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committer | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2012-09-05 10:22:45 -0400 |
commit | 593d0a3e9f813db910dc50574532914db21d09ff (patch) | |
tree | 12d8413ee57b4383ca8c906996ffe02be6d377a5 /arch/arm/mach-omap2/id.c | |
parent | 50e900417b8096939d12a46848f965e27a905e36 (diff) | |
parent | 4cb38750d49010ae72e718d46605ac9ba5a851b4 (diff) | |
download | blackbird-op-linux-593d0a3e9f813db910dc50574532914db21d09ff.tar.gz blackbird-op-linux-593d0a3e9f813db910dc50574532914db21d09ff.zip |
Merge commit '4cb38750d49010ae72e718d46605ac9ba5a851b4' into stable/for-linus-3.6
* commit '4cb38750d49010ae72e718d46605ac9ba5a851b4': (6849 commits)
bcma: fix invalid PMU chip control masks
[libata] pata_cmd64x: whitespace cleanup
libata-acpi: fix up for acpi_pm_device_sleep_state API
sata_dwc_460ex: device tree may specify dma_channel
ahci, trivial: fixed coding style issues related to braces
ahci_platform: add hibernation callbacks
libata-eh.c: local functions should not be exposed globally
libata-transport.c: local functions should not be exposed globally
sata_dwc_460ex: support hardreset
ata: use module_pci_driver
drivers/ata/pata_pcmcia.c: adjust suspicious bit operation
pata_imx: Convert to clk_prepare_enable/clk_disable_unprepare
ahci: Enable SB600 64bit DMA on MSI K9AGM2 (MS-7327) v2
[libata] Prevent interface errors with Seagate FreeAgent GoFlex
drivers/acpi/glue: revert accidental license-related 6b66d95895c bits
libata-acpi: add missing inlines in libata.h
i2c-omap: Add support for I2C_M_STOP message flag
i2c: Fall back to emulated SMBus if the operation isn't supported natively
i2c: Add SCCB support
i2c-tiny-usb: Add support for the Robofuzz OSIF USB/I2C converter
...
Diffstat (limited to 'arch/arm/mach-omap2/id.c')
-rw-r--r-- | arch/arm/mach-omap2/id.c | 57 |
1 files changed, 54 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 0389b3264abe..40373db649aa 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -44,12 +44,17 @@ int omap_type(void) if (cpu_is_omap24xx()) { val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); - } else if (cpu_is_am33xx()) { + } else if (soc_is_am33xx()) { val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); + } else if (soc_is_omap54xx()) { + val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); + val &= OMAP5_DEVICETYPE_MASK; + val >>= 6; + goto out; } else { pr_err("Cannot detect omap type!\n"); goto out; @@ -100,7 +105,7 @@ static u16 tap_prod_id; void omap_get_die_id(struct omap_die_id *odi) { - if (cpu_is_omap44xx()) { + if (cpu_is_omap44xx() || soc_is_omap54xx()) { odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); @@ -189,7 +194,7 @@ static void __init omap3_cpuinfo(void) cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; } else if (cpu_is_ti816x()) { cpu_name = "TI816X"; - } else if (cpu_is_am335x()) { + } else if (soc_is_am335x()) { cpu_name = "AM335X"; } else if (cpu_is_ti814x()) { cpu_name = "TI814X"; @@ -247,6 +252,17 @@ void __init omap3xxx_check_features(void) omap_features |= OMAP3_HAS_SDRC; /* + * am35x fixups: + * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as + * reserved and therefore return 0 when read. Unfortunately, + * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to + * mean that a feature is present even though it isn't so clear + * the incorrectly set feature bits. + */ + if (soc_is_am35xx()) + omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); + + /* * TODO: Get additional info (where applicable) * e.g. Size of L2 cache. */ @@ -502,6 +518,41 @@ void __init omap4xxx_check_revision(void) ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); } +void __init omap5xxx_check_revision(void) +{ + u32 idcode; + u16 hawkeye; + u8 rev; + + idcode = read_tap_reg(OMAP_TAP_IDCODE); + hawkeye = (idcode >> 12) & 0xffff; + rev = (idcode >> 28) & 0xff; + switch (hawkeye) { + case 0xb942: + switch (rev) { + case 0: + default: + omap_revision = OMAP5430_REV_ES1_0; + } + break; + + case 0xb998: + switch (rev) { + case 0: + default: + omap_revision = OMAP5432_REV_ES1_0; + } + break; + + default: + /* Unknown default to latest silicon rev as default*/ + omap_revision = OMAP5430_REV_ES1_0; + } + + pr_info("OMAP%04x ES%d.0\n", + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf)); +} + /* * Set up things for map_io and processor detection later on. Gets called * pretty much first thing from board init. For multi-omap, this gets |