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author | Richard Woodruff <r-woodruff2@ti.com> | 2010-02-22 22:09:08 -0700 |
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committer | Paul Walmsley <paul@pwsan.com> | 2010-02-24 12:15:02 -0700 |
commit | 358965d7bab9c70c11b64931da02667b161cb03a (patch) | |
tree | 884a13c783f9ba43cc5fe063c5fbeecde7804f58 /arch/arm/mach-omap2/dpll3xxx.c | |
parent | 91808a81fe7cc8a786b575ebc2d102c59d83c1a7 (diff) | |
download | blackbird-op-linux-358965d7bab9c70c11b64931da02667b161cb03a.tar.gz blackbird-op-linux-358965d7bab9c70c11b64931da02667b161cb03a.zip |
OMAP3 clock: introduce DPLL4 Jtype
DPLL4 for 3630 introduces a changed block called j type dpll, requiring
special divisor bits and additional reg fields. To allow for silicons to
use this, this is introduced as a flag and is enabled for 3630 silicon.
OMAP4 also has j type dpll for usb.
Tested with 3630 ZOOM3 and OMAP3430 ZOOM2
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vishwanath BS <Vishwanath.bs@ti.com>
[paul@pwsan.com: added some comments; updated copyrights and credits; fixed
some style issues]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/dpll3xxx.c')
-rw-r--r-- | arch/arm/mach-omap2/dpll3xxx.c | 67 |
1 files changed, 63 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 68268cd89e05..417c3caa05db 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -1,11 +1,14 @@ /* * OMAP3/4 - specific DPLL control functions * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Written by Paul Walmsley - * Testing and integration fixes by Jouni Högander + * Testing and integration fixes by Jouni Högander + * + * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth + * Menon * * Parts of this code are based on code written by * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu @@ -225,6 +228,47 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) return 0; } +/** + * lookup_dco_sddiv - Set j-type DPLL4 compensation variables + * @clk: pointer to a DPLL struct clk + * @dco: digital control oscillator selector + * @sd_div: target sigma-delta divider + * @m: DPLL multiplier to set + * @n: DPLL divider to set + * + * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" + * + * XXX This code is not needed for 3430/AM35xx; can it be optimized + * out in non-multi-OMAP builds for those chips? + */ +static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, + u8 n) +{ + unsigned long fint, clkinp, sd; /* watch out for overflow */ + int mod1, mod2; + + clkinp = clk->parent->rate; + fint = (clkinp / n) * m; + + if (fint < 1000000000) + *dco = 2; + else + *dco = 4; + /* + * target sigma-delta to near 250MHz + * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] + */ + clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ + mod1 = (clkinp * m) % (250 * n); + sd = (clkinp * m) / (250 * n); + mod2 = sd % 10; + sd /= 10; + + if (mod1 || mod2) + sd++; + *sd_div = sd; +} + /* * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly * @clk: struct clk * of DPLL to set @@ -259,6 +303,21 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) v &= ~(dd->mult_mask | dd->div1_mask); v |= m << __ffs(dd->mult_mask); v |= (n - 1) << __ffs(dd->div1_mask); + + /* + * XXX This code is not needed for 3430/AM35XX; can it be optimized + * out in non-multi-OMAP builds for those chips? + */ + if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) { + u8 dco, sd_div; + lookup_dco_sddiv(clk, &dco, &sd_div, m, n); + /* XXX This probably will need revision for OMAP4 */ + v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK + | OMAP3630_PERIPH_DPLL_SD_DIV_MASK); + v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK); + v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK); + } + __raw_writel(v, dd->mult_div1_reg); /* We let the clock framework set the other output dividers later */ @@ -536,7 +595,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk) v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); - if (v != OMAP3XXX_EN_DPLL_LOCKED) + if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) rate = clk->parent->rate; else rate = clk->parent->rate * 2; |