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| author | Rajendra Nayak <rnayak@ti.com> | 2012-04-27 16:35:52 +0530 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 19:18:50 -0700 |
| commit | 25f4214e388dda818765b670fb608f2e6467d877 (patch) | |
| tree | 7d93133ad7ab52df724461bc903a9d49aba08ddf /arch/arm/mach-omap2/clkt34xx_dpll3m2.c | |
| parent | 13a5b6228679456cbc47a8d50e6580063caf8058 (diff) | |
| download | blackbird-op-linux-25f4214e388dda818765b670fb608f2e6467d877.tar.gz blackbird-op-linux-25f4214e388dda818765b670fb608f2e6467d877.zip | |
ARM: OMAP3: clock: Cleanup !CONFIG_COMMON_CLK parts
Clean all #ifdef's added to OMAP3 clock code to make it COMMON clk
ready, not that CONFIG_COMMON_CLK is enabled.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: remove some ifdefs in mach-omap2/io.c]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt34xx_dpll3m2.c')
| -rw-r--r-- | arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index aeaaa87cca06..8e48c6d602e7 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -45,15 +45,10 @@ * Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); -#else -int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) -{ -#endif u32 new_div = 0; u32 unlock_dll = 0; u32 c; @@ -71,11 +66,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; sdrcrate = __clk_get_rate(sdrc_ick_p); -#ifdef CONFIG_COMMON_CLK clkrate = __clk_get_rate(hw->clk); -#else - clkrate = __clk_get_rate(clk); -#endif if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >> 1); else @@ -124,10 +115,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); -#ifndef CONFIG_COMMON_CLK - clk->rate = rate; -#endif - return 0; } |
