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| author | Rajendra Nayak <rnayak@ti.com> | 2012-09-22 02:24:17 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-09-22 10:52:56 -0600 |
| commit | 5dcc3b975e972989574c009457f0e333c342910d (patch) | |
| tree | 1e8c96d112b329fd5fface92d6a1a74d79f2a6ef /arch/arm/mach-omap2/clkt34xx_dpll3m2.c | |
| parent | 6ea74cb9853e923f8945586cd9ccdd42e6f00ba9 (diff) | |
| download | blackbird-op-linux-5dcc3b975e972989574c009457f0e333c342910d.tar.gz blackbird-op-linux-5dcc3b975e972989574c009457f0e333c342910d.zip | |
ARM: OMAP2+: clock: Remove all direct dereferencing of struct clk
While we move to Common Clk Framework (CCF), direct deferencing of struct
clk wouldn't be possible anymore. Hence get rid of all such instances
in the current clock code and use macros/helpers similar to the ones that
are provided by CCF.
While here also concatenate some strings split across multiple lines
which seem to be needed anyway.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: simplified some compound expressions; reformatted some
messages]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-omap2/clkt34xx_dpll3m2.c')
| -rw-r--r-- | arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c index d6e34dd9e7e7..0fd8b70201e4 100644 --- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c +++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c @@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) struct omap_sdrc_params *sdrc_cs0; struct omap_sdrc_params *sdrc_cs1; int ret; + unsigned long clkrate; if (!clk || !rate) return -EINVAL; @@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (validrate != rate) return -EINVAL; - sdrcrate = sdrc_ick_p->rate; - if (rate > clk->rate) - sdrcrate <<= ((rate / clk->rate) >> 1); + sdrcrate = __clk_get_rate(sdrc_ick_p); + clkrate = __clk_get_rate(clk); + if (rate > clkrate) + sdrcrate <<= ((rate / clkrate) >> 1); else - sdrcrate >>= ((clk->rate / rate) >> 1); + sdrcrate >>= ((clkrate / rate) >> 1); ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1); if (ret) @@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* * XXX This only needs to be done when the CPU frequency changes */ - _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ; + _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT; c += 1; /* for safety */ c *= SDRC_MPURATE_LOOPS; @@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (c == 0) c = 1; - pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, - validrate); + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", + clkrate, validrate); pr_debug("clock: SDRC CS0 timing params used:" " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n", sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, @@ -104,14 +106,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (sdrc_cs1) omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla, sdrc_cs1->actim_ctrlb, sdrc_cs1->mr); else omap3_configure_core_dpll( - new_div, unlock_dll, c, rate > clk->rate, + new_div, unlock_dll, c, rate > clkrate, sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); |
