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authorTony Lindgren <tony@atomide.com>2011-12-08 13:22:57 -0800
committerTony Lindgren <tony@atomide.com>2011-12-08 13:22:57 -0800
commit4c89aad9f4803875f7065e825badc9ba61922091 (patch)
treed0c60e673e527085aaddd76fb512311aa6159e40 /arch/arm/mach-omap2/Kconfig
parentdeee6d5359969a0ce4e2760cfd7b9f379bd5698a (diff)
parentff819da44258ca12b9f60dfd589884106e5a3129 (diff)
downloadblackbird-op-linux-4c89aad9f4803875f7065e825badc9ba61922091.tar.gz
blackbird-op-linux-4c89aad9f4803875f7065e825badc9ba61922091.zip
Merge branch 'for_3.3/pm/omap4-mpuss' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap4
Diffstat (limited to 'arch/arm/mach-omap2/Kconfig')
-rw-r--r--arch/arm/mach-omap2/Kconfig21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b6625130831d..50f43942c1aa 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -353,6 +353,27 @@ config OMAP3_SDRC_AC_TIMING
wish to say no. Selecting yes without understanding what is
going on could result in system crashes;
+config OMAP4_ERRATA_I688
+ bool "OMAP4 errata: Async Bridge Corruption"
+ depends on ARCH_OMAP4
+ select ARCH_HAS_BARRIERS
+ help
+ If a data is stalled inside asynchronous bridge because of back
+ pressure, it may be accepted multiple times, creating pointer
+ misalignment that will corrupt next transfers on that data path
+ until next reset of the system (No recovery procedure once the
+ issue is hit, the path remains consistently broken). Async bridge
+ can be found on path between MPU to EMIF and MPU to L3 interconnect.
+ This situation can happen only when the idle is initiated by a
+ Master Request Disconnection (which is trigged by software when
+ executing WFI on CPU).
+ The work-around for this errata needs all the initiators connected
+ through async bridge must ensure that data path is properly drained
+ before issuing WFI. This condition will be met if one Strongly ordered
+ access is performed to the target right before executing the WFI.
+ In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+ IO barrier ensure that there is no synchronisation loss on initiators
+ operating on both interconnect port simultaneously.
endmenu
endif
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