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| author | Paul Walmsley <paul@pwsan.com> | 2012-07-26 00:54:26 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2012-09-12 02:57:10 -0600 |
| commit | 7852ec0536ca39cefffc6301dc77f8ae55592926 (patch) | |
| tree | faa867a05d6571d5027b3fbfdf452678b3d35d38 /arch/arm/mach-omap1/clock_data.c | |
| parent | a032d33b65c89a781c871fd1def595fa6a69b52a (diff) | |
| download | blackbird-op-linux-7852ec0536ca39cefffc6301dc77f8ae55592926.tar.gz blackbird-op-linux-7852ec0536ca39cefffc6301dc77f8ae55592926.zip | |
ARM: OMAP: unwrap strings
Find and unwrap wrapped strings in the style:
pr_debug("clockdomain: hardware cannot set/clear wake up of "
"%s when %s wakes up\n", clkdm1->name, clkdm2->name);
Keeping these strings contiguous seems to be the current Linux kernel
policy.
The offending lines were found with the following command:
pcregrep -rnM '"\s*$\s*"' arch/arm/*omap*
While here, some messages have been clarified, some pr_warning(
... calls have been converted to pr_warn( ..., and some printk(KERN_*
... have been converted to pr_*.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap1/clock_data.c')
| -rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c007d80dfb62..243e8b2865f5 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -776,11 +776,10 @@ static struct clk_functions omap1_clk_functions = { static void __init omap1_show_rates(void) { - pr_notice("Clocking rate (xtal/DPLL1/MPU): " - "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); + pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); } u32 cpu_mask; @@ -848,8 +847,8 @@ int __init omap1_clk_init(void) if (cpu_is_omap16xx() && crystal_type == 2) ck_ref.rate = 19200000; - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " - "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), + pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", + omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); /* We want to be in syncronous scalable mode */ |
