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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-11 10:55:04 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-10-11 10:55:04 +0100 |
| commit | a0f0dd57f4a85310d9936f1770a0424b49fef876 (patch) | |
| tree | 2f85b8b67dda13d19b02ca39e0fbef921cb1cf8b /arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |
| parent | 2a552d5e63d7fa602c9a9a0717008737f55625a6 (diff) | |
| parent | 846a136881b8f73c1f74250bf6acfaa309cab1f2 (diff) | |
| download | blackbird-op-linux-a0f0dd57f4a85310d9936f1770a0424b49fef876.tar.gz blackbird-op-linux-a0f0dd57f4a85310d9936f1770a0424b49fef876.zip | |
Merge branch 'fixes' into for-linus
Conflicts:
arch/arm/kernel/smp.c
Diffstat (limited to 'arch/arm/mach-kirkwood/include/mach/bridge-regs.h')
| -rw-r--r-- | arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index a115142f8690..5c82b7dce4e2 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -13,37 +13,37 @@ #include <mach/kirkwood.h> -#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) #define CPU_CONFIG_ERROR_PROP 0x00000004 -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define CPU_RESET 0x00000002 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_LOW_OFF 0x0000 #define IRQ_MASK_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) -#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) +#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128) #define L2_WRITETHROUGH 0x00000010 -#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) +#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c) #define CGC_BIT_GE0 (0) #define CGC_BIT_PEX0 (2) #define CGC_BIT_USB0 (3) |
