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authorKrzysztof Hałasa <khc@pm.waw.pl>2009-11-15 18:02:10 +0100
committerKrzysztof Hałasa <khc@pm.waw.pl>2009-12-05 16:58:39 +0100
commited5b9fa0d1c5ad1e01ff56b9acd3ff52bc783f66 (patch)
treed3068a6963c1e15d039323462a399175942fc08c /arch/arm/mach-ixp4xx/include/mach/hardware.h
parentcba362221b12b102dff1f21b291fdc7b93e24a18 (diff)
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IXP4xx: Extend PCI MMIO indirect address space to 1 GB.
IXP4xx CPUs can indirectly access the whole 4 GB PCI MMIO address space (using the non-prefetch registers). Previously the available space depended on the CPU variant, since one of the IXP43x platforms needed more than the usual 128 MB. 1 GB should be enough for everyone, and if not, we can trivially increase it. Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
Diffstat (limited to 'arch/arm/mach-ixp4xx/include/mach/hardware.h')
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/hardware.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index f58a43a23966..f822b223b7e0 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -18,7 +18,13 @@
#define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */
+#define PCIBIOS_MAX_MEM 0x4FFFFFFF
+#else
+#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */
+#define PCIBIOS_MAX_MEM 0x4BFFFFFF
+#endif
/*
* We override the standard dma-mask routines for bouncing.
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